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Distributors for availability and specifications.
Supply Voltage (V
CC
)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Duration
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 4 sec)
Maximum Power Dissipation
@
25˚C
MTD56 (TSSOP) Package:
DS90CF583
−0.3V to +6V
−0.3V to (V
CC
+ 0.3V)
−0.3V to (V
CC
+ 0.3V)
−0.3V to (V
CC
+ 0.3V)
−0.3V to (V
CC
+ 0.3V)
Continuous
+150˚C
−65˚C to +150˚C
+260˚C
DS90CF584
1.61W
Package Derating:
DS90CF583
12.5 mW/˚C above +25˚C
DS90CF584
12.4 mW/˚C above +25˚C
This device does not meet 2000V ESD rating (Note 4) .
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Operating Free Air
Temperature (T
A
)
Receiver Input Range
Supply Noise Voltage (V
CC
)
Min
4.75
−10
0
Nom
5.0
+25
Max
5.25
+70
2.4
100
Units
V
˚C
V
mV
P-P
1.63W
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
V
IH
V
IL
V
OH
V
OL
V
CL
I
IN
I
OS
V
OD
∆V
OD
V
CM
∆V
CM
V
OH
V
OL
I
OS
I
OZ
V
TH
V
TL
I
IN
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Clamp Voltage
Input Current
Output Short Circuit Current
Differential Output Voltage
Change in V
OD
between
Complementary Output States
Common Mode Voltage
Change in V
CM
between
Complementary Output States
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
Output
TRI-STATE
®
Current
V
OUT
= 0V, R
L
= 100Ω
Power Down = 0V, V
OUT
= 0V or V
CC
V
CM
= +1.2V
−100
V
IN
= +2.4V
V
IN
= 0V
R
L
= 100Ω, C
L
= 5 pF,
Worst Case Pattern
(Figure
1, Figure 3)
R
L
= 100Ω, C
L
= 5 pF,
16 Grayscale Pattern
(Figure
2, Figure 3)
V
CC
= 5.5V
0.9
1.3
1.01
−2.9
−5
1.6
V
V
mA
µA
mV
mV
1.1
1.25 1.375
35
V
mV
I
OH
= −0.4 mA
I
OL
= 2 mA
I
CL
= −18 mA
V
IN
= V
CC
, GND, 2.5V or 0.4V
V
OUT
= 0V
R
L
= 100Ω
250
Conditions
Min
2.0
GND
3.8
4.9
0.1
−0.79
0.3
−1.5
Typ
Max
V
CC
0.8
Units
V
V
V
V
V
µA
mA
mV
mV
CMOS/TTL DC SPECIFICATIONS
±
5.1
±
10
−120
LVDS DRIVER DC SPECIFICATIONS
290
450
35
±
1
±
10
+100
LVDS RECEIVER DC SPECIFICATIONS
Differential Input High
Threshold
Differential Input Low Threshold
Input Current
±
10
±
10
49
51
70
40
41
55
63
64
84
55
55
67
µA
µA
mA
mA
mA
mA
mA
mA
TRANSMITTER SUPPLY CURRENT
I
CCTW
Transmitter Supply Current,
Worst Case
I
CCTG
Transmitter Supply Current,
16 Grayscale
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
3
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Electrical Characteristics
Symbol
I
CCTZ
Parameter
Transmitter Supply Current,
Power Down
RECEIVER SUPPLY CURRENT
I
CCRW
Receiver Supply Current,
Worst Case
I
CCRG
Receiver Supply Current,
16 Grayscale
I
CCRZ
Receiver Supply Current,
Power Down
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Conditions
Power Down = Low
Min
Typ
1
Max
25
Units
µA
TRANSMITTER SUPPLY CURRENT
C
L
= 8 pF,
Worst Case Pattern
(Figure
1, Figure 4)
C
L
= 8 pF,
16 Grayscale Pattern
(Figure
2, Figure 4)
Power Down = Low
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
64
70
110
35
37
55
1
77
85
140
55
55
67
10
mA
mA
mA
mA
mA
mA
µA
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2:
Typical values are given for V
CC
= 5.0V and T
A
= +25˚C.
Note 3:
Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V
OD
and
∆V
OD
).
Note 4:
ESD Rating: HBM (1.5 kΩ, 100 pF)
PLL V
CC
≥
1000V
All other pins
≥
2000V
EIAJ (0Ω, 200 pF)
≥
150V
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
LHLT
TCIT
TCCS
TCCD
TCIP
TCIH
TCIL
TSTC
THTC
TPDD
TPLLS
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
Parameter
LVDS Low-to-High Transition Time (Figure
3)
LVDS High-to-Low Transition Time (Figure
3)
TxCLK IN Transition Time (Figure
5)
TxOUT Channel-to-Channel Skew (Note 5) (Figure
6)
TxCLK IN to TxCLK OUT Delay
@
25˚C, V
CC
= 5.0V
(Figure
9)
TxCLK IN Period (Figure
7)
TxCLK IN High Time (Figure
7)
TxCLK IN Low Time (Figure
7)
TxIN Setup to TxCLK IN (Figure
7
)
TxIN Hold to TxCLK IN (Figure
7)
Transmitter Powerdown Delay (Figure
18)
Transmitter Phase Lock Loop Set (Figure
11)
Transmitter Output Pulse Position 0 (Figure
13)
Transmitter Output Pulse Position 1
Transmitter Output Pulse Position 2
Transmitter Output Pulse Position 3
Transmitter Output Pulse Position 4
Transmitter Output Pulse Position 5
Transmitter Output Pulse Position 6
−0.30
1.70
3.60
5.90
8.30
10.40
12.70
0
1/7 T
clk
2/7 T
clk
3/7 T
clk
4/7 T
clk
5/7 T
clk
6/7 T
clk
f = 65 MHz
15
0.35T
0.35T
5
2.5
T
0.5T
0.5T
3.5
1.5
100
10
0.30
2.50
4.50
6.75
9.00
11.10
13.40
50
0.65T
0.65T
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
3.5
Min
Typ
0.75
0.75
Max
1.5
1.5
8
350
8.5
Units
ns
ns
ns
ps
ns
Note 5:
This limit based on bench characterization.
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4
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
CLHT
CHLT
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RSKM
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time (Figure
4)
CMOS/TTL High-to-Low Transition Time (Figure
4)
RxCLK OUT Period
RxCLK OUT High Time
RxCLK OUT Low Time
RxOUT Setup to RxCLK OUT
RxOUT Hold to RxCLK OUT
RxCLK IN to RxCLK OUT Delay
@
25˚C, V
CC
= 5.0V
(Figure
10)
Receiver Phase Lock Loop Set (Figure
12)
RxIN Skew Margin (Note 6) (Figure
14)
Receiver Powerdown (Figure
17)
V
CC
= 5V, T
A
= 25˚C
600
1
10
ms
ps
µs
f = 65 MHz
f = 65 MHz
f = 65 MHz
f = 65 MHz
15
7.8
3.8
2.5
4.0
6.4
Min
Typ
2.5
2.0
T
9
5
4.2
5.2
10.7
Max
4.0
3.5
50
Units
ns
ns
ns
ns
ns
ns
ns
ns
Note 6:
Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
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