If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
−0.3V to +4V
CMOS/TTL Input Voltage
−0.3V to (V
CC
+ 0.3V)
CMOS/TTL Output Voltage
−0.3V to (V
CC
+ 0.3V)
LVDS Receiver Input Voltage
−0.3V to (V
CC
+ 0.3V)
LVDS Driver Output Voltage
−0.3V to (V
CC
+ 0.3V)
LVDS Output Short
Circuit Duration
Continuous
Junction Temperature
+150°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature
(Soldering, 4 sec.)
+260°C
Maximum Package Power Dissipation @ +25°C
MTD48 (TSSOP) Package:
DS90CR215
DS90CR216
Package Derating
DS90CR215
DS90CR216
ESD Rating
(HBM, 1.5 kΩ, 100 pF)
1.98 W
1.89 W
16 mW/°C above +25°C
15 mW/°C above +25°C
> 7 kV
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
Operating Free Air
Temperature (T
A
)
Receiver Input Range
Supply Noise Voltage (V
CC
)
3.0
No Max Units
m
3.3 3.6
V
−40 +25 +85 °C
0
2.4
V
100 mV
PP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
V
IH
V
IL
V
OH
V
OL
V
CL
I
IN
I
OS
V
OD
ΔV
OD
V
OS
ΔV
OS
I
OS
I
OZ
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Clamp Voltage
Input Current
Output Short Circuit Current
Differential Output Voltage
Change in V
OD
between Complimentary
Output States
Offset Voltage (Note 4)
Change in V
OS
between Complimentary Output
States
Output Short Circuit Current
Output TRI-STATE
®
Current
V
OUT
= 0V,
R
L
= 100Ω
PWR DWN = 0V,
V
OUT
= 0V or V
CC
LVDS RECEIVER DC SPECIFICATIONS
V
TH
V
TL
I
IN
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V
IN
= +2.4V, V
CC
= 3.6V
V
IN
= 0V, V
CC
= 3.6V
TRANSMITTER SUPPLY CURRENT
V
CM
= +1.2V
−100
±10
±10
+100
mV
mV
μA
μA
±1
±10
μA
−3.5
1.125
1.25
I
OH
= −0.4 mA
I
OL
= 2 mA
I
CL
= −18 mA
V
IN
= V
CC
, GND,
2.5V or 0.4V
V
OUT
= 0V
R
L
= 100Ω
250
-60
290
−120
450
35
1.375
35
−5
mA
mV
mV
V
mV
mA
LVDS DRIVER DC SPECIFICATIONS
Conditions
Min
2.0
GND
2.7
3.3
0.06
−0.79
±5.1
0.3
−1.5
±10
Typ
Max
V
CC
0.8
Units
V
V
V
V
V
μA
CMOS/TTL DC SPECIFICATIONS
3
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DS90CR215/DS90CR216
Symbol
I
CCTW
Parameter
Transmitter Supply Current Worst Case (with
Loads)
Conditions
R
L
= 100Ω,
C
L
= 5 pF,
Worst Case Pattern
(Figures
1, 2)
, T
A
= −10°C to +70°C
R
L
= 100Ω,
C
L
= 5 pF,
Worst Case Pattern
(Figures
1, 2)
, T
A
= −40°C to +85°C
f = 32.5 MHz
f = 37.5 MHz
f = 66 MHz
Min
Typ
31
32
37
Max
45
50
55
Units
mA
mA
mA
f = 40 MHz
f = 66 MHz
38
42
51
55
mA
mA
I
CCTZ
Transmitter Supply Current Power Down
PWR DWN = Low
Driver Outputs in TRI-STATE
under Powerdown Mode
C
L
= 8 pF,
Worst Case Pattern
(Figures
1, 3)
, T
A
= −10°C to +70°C
C
L
= 8 pF,
Worst Case Pattern
(Figures
1, 3)
, T
A
= −40°C to +85°C
f = 32.5 MHz
f = 37.5 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
10
55
μA
RECEIVER SUPPLY CURRENT
I
CCRW
Receiver Supply Current Worst Case
49
53
78
55
78
65
70
105
82
105
mA
mA
mA
mA
mA
I
CCRZ
Receiver Supply Current Power Down
PWR DWN = Low
Receiver Outputs Stay Low during
Powerdown Mode
10
55
μA
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2:
Typical values are given for V
CC
= 3.3V and T
A
= +25°C.
Note 3:
Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V
OD
and
ΔV
OD
).
Note 4:
V
OS
previously referred as V
CM
.
Transmitter Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol
LLHT
LHLT
TCIT
TCCS
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
Parameter
LVDS Low-to-High Transition Time (Figure
2)
LVDS High-to-Low Transition Time (Figure
2)
TxCLK IN Transition Time (Figure
4)
TxOUT Channel-to-Channel Skew (Figure
5)
Transmitter Output Pulse Position for Bit0
(Note 7) (Figure
16)
Transmitter Output Pulse Position for Bit1
Transmitter Output Pulse Position for Bit2
Transmitter Output Pulse Position for Bit3
Transmitter Output Pulse Position for Bit4
Transmitter Output Pulse Position for Bit5
Transmitter Output Pulse Position for Bit6
Transmitter Output Pulse Position for Bit0
(Note 6) (Figure
16)
Transmitter Output Pulse Position for Bit1
Transmitter Output Pulse Position for Bit2
Transmitter Output Pulse Position for Bit3
Transmitter Output Pulse Position for Bit4
f = 66 MHz
f = 40 MHz
−0.4
3.1
6.5
10.2
13.7
17.3
21.0
−0.4
1.8
4.0
6.2
8.4
250
0
3.3
6.8
10.4
13.9
17.6
21.2
0
2.2
4.4
6.6
8.8
0.4
4.0
7.6
11.0
14.6
18.2
21.8
0.3
2.5
4.7
6.9
9.1
Min
Typ
0.5
0.5
Max
1.5
1.5
5
Units
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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4
DS90CR215/DS90CR216
Symbol
TPPos5
TPPos6
TCIP
TCIH
TCIL
TSTC
THTC
TCCD
TPLLS
TPDD
Parameter
Transmitter Output Pulse Position for Bit5
Transmitter Output Pulse Position for Bit6
TxCLK IN Period (Figure
6)
TxCLK IN High Time (Figure
6)
TxCLK IN Low Time (Figure
6)
TxIN Setup to TxCLK IN (Figure
6)
TxIN Hold to TxCLK IN (Figure
6)
TxCLK IN to TxCLK OUT Delay @ 25°C,V
CC
=3.3V (Figure
8)
Transmitter Phase Lock Loop Set (Figure
10)
Transmitter Powerdown Delay (Figure
14)
Min
10.6
12.8
15
0.35T
0.35T
2.5
0
3
Typ
11.0
13.2
T
0.5T
0.5T
Max
11.3
13.5
50
0.65T
0.65T
Units
ns
ns
ns
ns
ns
ns
ns
3.7
5.5
10
100
ns
ms
ns
Receiver Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol
CLHT
CHLT
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time (Figure
3)
CMOS/TTL High-to-Low Transition Time (Figure
3)
Receiver Input Strobe Position for Bit 0 (Note 7)(Figure
17)
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
Receiver Input Strobe Position for Bit 0 (Note 6)(Figure
17)
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 5) (Figure
18)
RxCLK OUT Period (Figure
7)
RxCLK OUT High Time (Figure
7)
RxCLK OUT Low Time (Figure
7)
RxOUT Setup to RxCLK OUT (Figure
7)
RxOUT Hold to RxCLK OUT (Figure
7)
RxCLK IN to RxCLK OUT Delay (Figure
9)
Receiver Phase Lock Loop Set (Figure
11)
Receiver Powerdown Delay (Figure
15)
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 66 MHz
f = 40 MHz
1.0
4.5
8.1
11.6
15.1
18.8
22.5
0.7
2.9
5.1
7.3
9.5
11.7
13.9
490
400
15
6.0
4.0
10.0
6.0
6.5
2.5
6.0
2.5
4.0
5.0
T
10.0
6.1
13.0
7.8
14.0
8.0
8.0
4.0
6.7
6.6
8.0
9.0
10
1
50
Min
Typ
2.2
2.2
1.4
5.0
8.5
11.9
15.6
19.2
22.9
1.1
3.3
5.5
7.7
9.9
12.1
14.3
Max
5.0
5.0
2.15
5.8
9.15
12.6
16.3
19.9
23.6
1.4
3.6
5.8
8.0
10.2
12.4
14.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
μs
Note 5:
Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference
(both dependent on type/length of cable), and clock jitter less than 250 ps.
Note 6:
The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.
Note 7:
The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
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