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DS90LV011A 3V LVDS Single High Speed Differential Driver
April 6, 2009
DS90LV011A
3V LVDS Single High Speed Differential Driver
General Description
The DS90LV011A is a single LVDS driver device optimized
for high data rate and low power applications. The
DS90LV011A is a current mode driver allowing power dissi-
pation to remain low even at high frequency. In addition, the
short circuit fault current is also minimized. The device is de-
signed to support data rates in excess of 400Mbps (200MHz)
utilizing Low Voltage Differential Signaling (LVDS) technolo-
gy.
The device is in a 5-lead small outline transistor package. The
LVDS outputs have been arranged for easy PCB layout. The
differential driver outputs provide low EMI with its typical low
output swing of 350 mV. The DS90LV011A can be paired with
its companion single line receiver, the DS90LV012A, or with
any of National's LVDS receivers, to provide a high-speed
LVDS interface.
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
Conforms to TIA/EIA-644-A Standard
>400Mbps (200MHz) switching rates
700 ps (100 ps typical) maximum differential skew
1.5 ns maximum propagation delay
Single 3.3V power supply
±350 mV differential signaling
Power Off Protection (outputs in TRI-STATE)
Pinout simplifies PCB layout
Low power dissipation (23 mW @ 3.3V typical)
SOT-23 5-lead package
SOT-23 version pin compatible with SN65LVDS1
Fabricated with advanced CMOS process technology
Industrial temperature operating range
(−40°C to +85°C)
Connection Diagram
20014922
(Top View)
Order Number DS90LV011ATMF
See NS Package Number MF05A
Functional Diagram
20014902
© 2009 National Semiconductor Corporation
200149
www.national.com
DS90LV011A
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
DD
)
−0.3V to +4V
LVCMOS input voltage (TTL IN)
−0.3V to +3.6V
LVDS output voltage (OUT±)
−0.3V to +3.9V
LVDS output short circuit current
24mA
Maximum Package Power Dissipation @ +25°C
MF Package
902 mW
Derate MF Package
7.22 mW/°C above +25°C
Thermal Resistance (θ
JA
)
Storage Temperature
Lead Temperature – Soldering
138.5°C/Watt
−65°C to +150°C
+260°C (4 sec.)
Maximum Junction Temperature
ESD Ratings
HBM (1.5 kΩ, 100 pF)
EIAJ (0
Ω,
200 pF)
CDM (0
Ω,
0 pF)
IEC direct (330
Ω,
150 pF)
+150°C
≥
9kV
≥
900V
≥
2000V
≥
4kV
Recommended Operating
Conditions
Supply Voltage (V
DD
)
Temperature (T
A
)
Min
3.0
-40
Typ
3.3
+25
Max
3.6
+85
Units
V
°C
Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3, 8)
Symbol
|V
OD
|
ΔV
OD
V
OS
ΔV
OS
I
OFF
I
OS
I
OSD
C
OUT
V
IH
V
IL
I
IH
I
IL
V
CL
C
IN
I
DD
Parameter
Output Differential Voltage
V
OD
Magnitude Change
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current (Note
4)
Differential Output Short Circuit
Current (Note 4)
Output Capacitance
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Clamp Voltage
Input Capacitance
Power Supply Current
No Load
R
L
= 100Ω
V
IN
= V
DD
or GND
V
DD
V
IN
= 3.3V or 2.4V
V
IN
= GND or 0.5V
I
CL
= −18 mA
−1.5
TTL IN
2.0
GND
±2
±1
−0.6
3
5
7
8
10
Conditions
R
L
= 100Ω
(Figure
1
and
Figure 2)
R
L
= 100Ω
(Figure
1)
V
OUT
= 3.6V or GND, V
DD
= 0V
V
OUT+
and V
OUT−
= 0V
V
OD
= 0V
Pin
OUT+,
OUT−
Min
250
1.125
0
Typ
350
3
1.22
1
±1
−6
−5
3
V
DD
0.8
±10
±10
Max
450
35
1.375
25
±10
−24
−12
Units
mV
mV
V
mV
μA
mA
mA
pF
V
V
μA
μA
V
pF
mA
mA
Switching Characteristics
Over Supply Voltage and Operating Temperature Ranges, unless otherwise specified. (Notes 3, 5, 6, 7)
Symbol
t
PHLD
t
PLHD
t
SKD1
t
SKD3
t
SKD4
t
TLH
t
THL
f
MAX
Parameter
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Pulse Skew |t
PHLD
− t
PLHD
| (Note 9)
Differential Part to Part Skew (Note 10)
Differential Part to Part Skew (Note 11)
Transition Low to High Time
Transition High to Low Time
Maximum Operating Frequency (Note 12)
Conditions
R
L
= 100Ω,
C
L
= 15 pF
(Figure
3
and
Figure 4)
Min
0.3
0.3
0
0
0
0.2
0.2
200
Typ
1.0
1.1
0.1
0.2
0.4
0.5
0.5
250
Max
1.5
1.5
0.7
1.0
1.2
1.0
1.0
Units
ns
ns
ns
ns
ns
ns
ns
MHz
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
www.national.com
2
DS90LV011A
Note 2:
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V
OD
.
Note 3:
All typicals are given for: V
DD
= +3.3V and T
A
= +25°C.
Note 4:
Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only.
Note 5:
These parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage,
temperature) ranges.
Note 6:
C
L
includes probe and fixture capacitance.
Note 7:
Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50Ω,
t
r
≤
1 ns, t
f
≤
1 ns (10%-90%).
Note 8:
The DS90LV011A is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers outputs.
Note 9:
t
SKD1
, |t
PHLD
− t
PLHD
|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel.
Note 10:
t
SKD3
, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same V
DD
and within 5°C of each other within the operating temperature range.
Note 11:
t
SKD4
, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices over recommended
operating temperature and voltage ranges, and across process distribution. t
SKD4
is defined as |Max − Min| differential propagation delay.
Note 12:
f
MAX
generator input conditions: t
r
= t
f
< 1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45%/55%, V
OD
> 250mV. The parameter
is guaranteed by design. The limit is based on the statistical analysis of the device over the PVT range by the transitions times (t
TLH
and t
THL
).
Parameter Measurement Information
20014903
FIGURE 1. Differential Driver DC Test Circuit
20014924
FIGURE 2. Differential Driver Full Load DC Test Circuit
20014904
FIGURE 3. Differential Driver Propagation Delay and Transition Time Test Circuit
3
www.national.com
DS90LV011A
20014905
FIGURE 4. Differential Driver Propagation Delay and Transition Time Waveforms
Application Information
TABLE 1. Device Pin Descriptions
Package Pin Number
SOT23
5
4
3
2
1
Pin Name
TTL IN
OUT+
OUT−
GND
V
DD
Description
LVTTL/LVCMOS driver input pins
Non-inverting driver output pin
Inverting driver output pin
Ground pin
Power supply pin, +3.3V ± 0.3V
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4
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