1 to 10 LVDS Data/Clock Distributor
July 2001
DS90LV110T
1 to 10 LVDS Data/Clock Distributor
General Description
DS90LV110 is a 1 to 10 data/clock distributor utilizing LVDS
(Low Voltage Differential Signaling) technology for low
power, high speed operation. Data paths are fully differential
from input to output for low noise generation and low pulse
width distortion. The design allows connection of 1 input to
all 10 outputs. LVDS I/O enable high speed data transmis-
sion for point-to-point interconnects. This device can be used
as a high speed differential 1 to 10 signal distribution / fanout
replacing multi-drop bus applications for higher speed links
with improved signal quality. It can also be used for clock
distribution up to 400MHz.
The DS90LV110 accepts LVDS signal levels, LVPECL levels
directly or PECL with attenuation networks.
The LVDS outputs can be put into TRI-STATE by use of the
enable pin.
For more details, please refer to the Application Information
section of this datasheet.
Features
n
Low jitter 800 Mbps fully differential data path
n
145 ps (typ) of pk-pk jitter with PRBS = 2
23
−1 data
pattern at 800 Mbps
n
Single +3.3 V Supply
n
Less than 413 mW (typ) total power dissipation
n
Balanced output impedance
n
Output channel-to-channel skew is 35ps (typ)
n
Differential output voltage (V
OD
) is 320mV (typ) with
100Ω termination load.
n
LVDS receiver inputs accept LVPECL signals
n
Fast propagation delay of 2.8 ns (typ)
n
Receiver input threshold
<
±
100 mV
n
28 lead TSSOP package
n
Conforms to ANSI/TIA/EIA-644 LVDS standard
Connection Diagram
Block Diagram
10133705
Order Number DS90LV110TMTC
See NS Package Number MTC28
10133701
© 2001 National Semiconductor Corporation
DS101337
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DS90LV110T
Absolute Maximum Ratings
(Note 1)
Package Derating
28L TSSOP
θ
JA
28L TSSOP
ESD Rating:
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
103.4 ˚C/Watt
9.67 mW/˚C above +25˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
DD
-V
SS
)
LVCMOS/LVTTL Input Voltage
(EN)
LVDS Receiver Input Voltage
(IN+, IN−)
LVDS Driver Output Voltage
(OUT+, OUT−)
Junction Temperature
Storage Temperature Range
Lead Temperature
(Soldering, 4 sec.)
Maximum Package Power Dissipation at 25˚C
28L TSSOP
1.209 W
+260˚C
−0.3V to +4V
−0.3V to (V
CC
+ 0.3V)
>
4 kV
>
250 V
−0.3V to +4V
−0.3V to +4V
+150˚C
−65˚C to +150˚C
Recommended Operating
Conditions
Min Typ Max Units
Supply Voltage (V
DD
- V
SS
)
Receiver Input Voltage
Operating Free Air Temperature
3.0
0
-40
3.3
3.6
V
DD
+25 +85
V
V
˚C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
V
IH
V
IL
I
IH
I
IL
V
CL
V
OD
∆V
OD
V
OS
∆V
OS
I
OZ
I
OFF
I
SA
,I
SB
I
SAB
V
TH
V
TL
V
CMR
I
IN
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Clamp Voltage
Differential Output Voltage
V
IN
= 3.6V or 2.0V; V
DD
= 3.6V
V
IN
= 0V or 0.8V; V
DD
= 3.6V
I
CL
= −18 mA
R
L
= 100Ω
R
L
= 100Ω, V
DD
= 3.3V, T
A
= 25˚C
Change in V
OD
between Complimentary Output States
Offset Voltage (Note 3)
Change in V
OS
between Complimentary Output States
Output TRI-STATE Current
Power-Off Leakage Current
Output Short Circuit Current
Both Outputs Shorted (Note 4)
Differential Input High Threshold
Differential Input Low Threshold
Common Mode Voltage Range
Input Current
EN = 0V,
V
OUT
= V
DD
or GND
V
DD
= 0V; V
OUT
= 3.6V or GND
V
OUT+
OR V
OUT−
= 0V or V
DD
V
OUT+
= V
OUT−
V
CM
= +0.05V or +1.2V or +3.25V,
V
DD
= 3.3V
V
ID
= 100mV, V
DD
= 3.3V
V
IN
= +3.0V, V
DD
= 3.6V or 0V
V
IN
= 0V, V
DD
= 3.6V or 0V
−100
0.05
1.125
1.25
250
260
Conditions
Min
2.0
V
SS
Typ
Max
V
DD
0.8
Units
V
V
µA
µA
V
mV
mV
|mV|
V
|mV|
µA
µA
|mA|
|mA|
mV
mV
3.25
V
µA
µA
LVCMOS/LVTTL DC SPECIFICATIONS (EN)
±
7
±
7
−0.8
320
320
±
20
±
20
−1.5
450
425
35
1.375
35
LVDS OUTPUT DC SPECIFICATIONS (OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9, OUT10)
±
1
±
1
12
6
0
0
±
10
±
10
24
12
+100
LVDS RECEIVER DC SPECIFICATIONS (IN)
±
1
±
1
±
10
±
10
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2
DS90LV110T
Electrical Characteristics
Symbol
SUPPLY CURRENT
I
CCD
Total Supply Current
Parameter
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Conditions
R
L
= 100Ω, C
L
= 5 pF, 400 MHz,
EN = High
No Load, 400 MHz, EN = High
80
15
125
29
mA
mA
Min
Typ
125
Max
195
Units
mA
I
CCZ
TRI-STATE Supply Current
EN = Low
Note 1:
“Absolute Maximum Ratings” are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2:
All typical are given for V
CC
= +3.3V and T
A
= +25˚C, unless otherwise stated.
Note 3:
V
OS
is defined as (V
OH
+ V
OL
) / 2.
Note 4:
Only one output can be shorted at a time. Don’t exceed the package absolute maximum rating.
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
T
LHT
T
HLT
T
DJ
T
RJ
T
PLHD
T
PHLD
T
SKEW
T
CCS
T
PHZ
T
PLZ
T
PZH
T
PZL
Parameter
Conditions
Min
Typ
390
390
145
2.8
2.2
2.2
2.8
2.8
20
35
3.0
1.8
10.0
7.0
3.6
3.6
340
91
6.0
6.0
23.0
23.0
Max
550
550
Units
ps
ps
ps
ps
ns
ns
ps
ps
ns
ns
ns
ns
Output Low-to-High Transition Time, 20% to 80%,
Figure 4
(Note 5)
Output High-to-Low Transition Time, 80% to 20%,
Figure 4
(Note 5)
LVDS Data Jitter, Deterministic
(Peak-to-Peak)(Note 6)
LVDS Clock Jitter, Random (Note 6)
Propagation Low to High Delay,
Figure 5
Propagation High to Low Delay,
Figure 5
Pulse Skew |T
PLHD
- T
PHLD
| (Note 5)
Output Channel-to-Channel Skew,
Figure 6
(Note 5)
Disable Time (Active to TRI-STATE) High to Z,
Figure 1
Disable Time (Active to TRI-STATE) Low to Z,
Figure 1
Enable Time (TRI-STATE to Active) Z to High,
Figure 1
Enable Time (TRI-STATE to Active) Z to Low,
Figure 1
V
ID
= 300mV; PRBS=2
23
-1 data;
V
CM
= 1.2V at 800 Mbps (NRZ)
V
ID
= 300mV; V
CM
= 1.2V
at 400 MHz clock
Note 5:
The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage and
temperature) range.
Note 6:
The measurement used the following equipment and test setup: HP8133A pattern/pulse generator), 5 feet of RG-142 cable with DUT test board and
HP83480A (digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with the RG-142 cable exhibit a T
DJ
= 26ps and T
RJ
= 1.3 ps
3
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DS90LV110T
AC Timing Diagrams
10133704
FIGURE 1. Output active to TRI-STATE and TRI-STATE to active output time
10133715
FIGURE 2. LVDS Driver TRI-STATE Circuit
10133706
FIGURE 3. LVDS Output Load
10133709
FIGURE 4. LVDS Output Transition Time
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4
DS90LV110T
AC Timing Diagrams
(Continued)
10133707
FIGURE 5. Propagation Delay Low-to-High and High-to-Low
10133708
FIGURE 6. Output 1 to 10 Channel-to-Channel Skew
5
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