DS90UB913Q, DS90UB914Q
www.ti.com
SNLS420B – JULY 2012 – REVISED APRIL 2013
DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and
Deserializer with Bidirectional Control Channel
Check for Samples:
DS90UB913Q, DS90UB914Q
1
FEATURES
10 MHz to 100 MHz Input Pixel Clock Support
Single Differential Pair Interconnect
Programmable Data Payload:
– 10 bit Payload up to 100Mhz
– 12 bit Payload up to 75MHz
Continuous Low Latency Bidirectional Control
Interface Channel with I
2
C support@400kHz
2:1 Multiplexer to Choose Between Two Input
Imagers
Embedded Clock With DC Balanced Coding to
Support AC-Coupled Interconnects
Capable of Driving up to 25 Meters Shielded
Twisted-pair
Receive Equalizer Automatically Adapts for
Changes in Cable Loss
4 Dedicated General Purpose Input (GPI)/
Output (GPO)
LOCK Output Reporting Pin and AT-SPEED
BIST Diagnosis Feature to Validate Link
Integrity
1.8V, 2.8V or 3.3V Compatible Parallel Inputs
on Serializer
Single Power Supply at 1.8V
ISO 10605 and IEC 61000-4-2 ESD Compliant
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
Temperature Range
−40°C
to +105°C
Small Serializer Footprint (5mm x 5mm)
EMI/EMC Mitigation - Deserializer
– Programmable Spread Spectrum (SSCG)
Outputs.
– Receiver Staggered Outputs
DESCRIPTION
The DS90UB913Q/DS90UB914Q chipset offers a
FPD-Link III interface with a high-speed forward
channel and a bidirectional control channel for data
transmission over a single differential pair. The
DS90UB913Q/914Q chipsets incorporate differential
signaling on both the high-speed forward channel and
bidirectional control channel data paths. The
Serializer/ Deserializer pair is targeted for
connections between imagers and video processors
in an ECU (Electronic Control Unit). This chipset is
ideally suited for driving video data requiring up to 12
bit pixel depth plus two synchronization signals along
with bidirectional control channel bus.
There is a multiplexer at the Deserializer to choose
between two input imagers. The Deserializer can
have only one active input imager. The primary video
transport converts 10/12 bit data over a single high-
speed serial stream, along with a separate low
latency bidirectional control channel transport that
accepts control information from an I2C port and is
independent of video blanking period.
Using TI’s embedded clock technology allows
transparent full-duplex communication over a single
differential pair, carrying asymmetrical bidirectional
control channel information in both directions. This
single serial stream simplifies transferring a wide data
bus over PCB traces and cable by eliminating the
skew problems between parallel data and clock
paths. This significantly saves system cost by
narrowing data paths that in turn reduce PCB layers,
cable width, and connector size and pins. In addition,
the Deserializer inputs provide adaptive equalization
to compensate for loss from the media over longer
distances. Internal DC balanced encoding/decoding is
used to support AC-Coupled interconnects. The
Serializer is offered in a 32-pin WQFN package and
the Deserializer is offered in a 48-pin WQFN
package.
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APPLICATIONS
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Front or Rear View Camera for Collision
Mitigation
Surround View for Parking Assistance
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2012–2013, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS90UB913Q, DS90UB914Q
SNLS420B – JULY 2012 – REVISED APRIL 2013
www.ti.com
Typical Application Diagram
Parallel
Data In
10 or 12
FPD-Link III
Parallel
Data Out
10 or 12
2
2
Megapixel
Imager/Sensor
HSYNC,
VSYNC
DS90UB913Q
DS90UB914Q
4
GPO
2
Bidirectional
Control Bus
Bidirectional
Control Channel
Serializer
Deserializer
HSYNC,
VSYNC
4
GPIO
2
Bidirectional
Control Bus
DSP, FPGA/
µ-Processor/
ECU
Figure 1. Typical Application Circuit
Block Diagrams
10
or
12
10 or
12
Serializer
Encoder
DIN
HSYNC
VSYNC
GPO[3:0]
DOUT-
PCLK
PLL
Clock
Gen
2:1
RIN0-
RIN1+
CDR
RIN1-
PDB
Timing and
Control
PDB
BISTEN
OEN
Timing and
Control
Clock
Gen
Adaptive Eq.
Output Latch
Input Latch
Deserializer
Decoder
R
T
R
T
DOUT+
RIN0+ R
T
R
T
ROUT
HSYNC
VSYNC
4
4
GPIO[3:0]
PCLK
LOCK
PASS
Decoder
Encoder
I2C Controller
FIFO
SEL
I2C
Controller
SDA
SCL
IDx[0]
IDx[1]
Decoder
SCL
ID[x]
MODE
MODE
DS90UB913Q - SERIALIZER
DS90UB914Q - DESERIALIZER
Figure 2. Block Diagram
DS90UB913Q
Serializer
Camera Data
10 or 12
DOUT+
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
PCLK
DS90UB914Q
Deserializer
FPD-Link III
RIN+
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
PCLK
Camera Data
10 or 12
DATA
HSYNC
VSYNC
Pixel Clock
Image
Sensor
DATA
HSYNC
VSYNC
Pixel Clock
DOUT-
RIN-
Bi-Directional
Control Channel
Encoder
FIFO
SDA
ECU Module
4
GPO[3:0]
SDA
GPO[3:0]
SDA
SCL
GPIO[3:0]
SDA
SCL
4
GPIO[3:0]
SDA
SCL
Microcontroller
Camera Unit
SCL
Figure 3. Application Block Diagram
2
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links:
DS90UB913Q DS90UB914Q
DS90UB913Q, DS90UB914Q
www.ti.com
SNLS420B – JULY 2012 – REVISED APRIL 2013
24
23
22
21
20
19
18
16
15
14
12
11
10
6
7
RES
8
MODE
ID[x]
VDDIO
DIN[6]
25
GPO[2]/
CLKOUT
17
GPO[3]/
CLKIN
DIN[4]
DIN[3]
DIN[5]
DIN[2]
DIN[1]
DIN[0]
DAP = GND
GPO[1]
26
GPO[0]
DIN[7]
27
VDDCML
VDDD
29
DIN[8]
DIN[9]
DS90UB913Q
32-Pin WQFN
(Top View)
28
13
DOUT+
DOUT-
30
VDDT
VDDPLL
DIN[10]
DIN[11]
31
32
PDB
1
2
3
4
5
PCLK
HSYNC
VSYNC
SCL
Serializer - DS90UB913Q — Top View
DS90UB913Q SERIALIZER PIN DESCRIPTIONS
Pin Name
DIN[0:11]
Pin No.
19,20,21,22,
23,24,26,27,
29,30,31,32
1
I/O, Type
Inputs,
LVCMOS
w/ pull down
Inputs,
LVCMOS
w/ pull down
Inputs,
LVCMOS
w/ pull down
Parallel Data Inputs.
Description
LVCMOS PARALLEL INTERFACE
HSYNC
Horizontal SYNC Input
VSYNC
2
Vertical SYNC Input
PCLK
3
Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.
w/ pull down
Output,
LVCMOS
General-purpose output pins can be configured as outputs; used to control and
respond to various commands. GPO[0:1] can be configured to be the outputs for input
signals coming from GPIO[0:1] pins on the Deserializer or can be configured to be
outputs of the local register on the Serializer.
GPO2 pin can be configured to be the output for input signal coming from the GPIO2
pin on the Deserializer or can be configured to be the output of the local register on
the Serializer. It can also be configured to be the output clock pin when the
DS90UB913Q device is used in the External Oscillator mode. See
Applications
Information
for a detailed description of the DS90UB913/914Q chipsets working with
the external oscillator.
GENERAL PURPOSE OUTPUT (GPO)
GPO[1:0]
16,15
GPO[2]/CLKOUT
17
Output,
LVCMOS
SDA
9
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SNLS420B – JULY 2012 – REVISED APRIL 2013
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DS90UB913Q SERIALIZER PIN DESCRIPTIONS (continued)
Pin Name
GPO[3]/CLKIN
Pin No.
18
I/O, Type
Input/Output,
LVCMOS
Description
GPO3 can be configured to be the output for input signals coming from the GPIO3 pin
on the Deserializer or can be configured to be the output of the local register setting
on the Serializer. It can also be configured to be the input clock pin when the
DS90UB913Q Serializer is working with an external oscillator. See
Applications
Information
section for a detailed description of the DS90UB913/914Q chipsets
working with an external oscillator.
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to V
DDIO
.
Data line for the bidirectional control bus communication
SDA requires an external pull-up resistor to V
DDIO
.
BIDIRECTIONAL CONTROL BUS - I
2
C COMPATIBLE
SCL
SDA
4
5
Input/Output,
Open Drain
Input/Output,
Open Drain
MODE
8
Device mode select
Input, LVCMOS Resistor to Ground and 10 kΩ pull-up to 1.8V rail. MODE pin on the Serializer can be
w/ pull down
used to select whether the system is running off the PCLK from the imager or an
external oscillator. See details in
Table 5
Input, analog
Device ID Address Select
The ID[x] pin on the Serializer is used to assign the I2C device address. Resistor to
Ground and 10 kΩ pull-up to 1.8V rail. See
Table 7
ID[x]
6
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
Input, LVCMOS
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,
w/ pull down
the PLL is shutdown, and IDD is minimized. Programmed control register data are
NOT retained and reset to default values
Input, LVCMOS Reserved.
w/ pull down
This pin MUST be tied LOW.
Input/Output,
CML
Input/Output,
CML
Power, Analog
Power, Analog
Power, Analog
Power, Digital
Power, Digital
Ground, DAP
VSS
DAP
Non-inverting differential output, bidirectional control channel input. The interconnect
must be AC Coupled with a 100 nF capacitor.
Inverting differential output, bidirectional control channel input. The interconnect must
be AC Coupled with a 100 nF capacitor.
PLL Power, 1.8V ±5%
Tx Analog Power, 1.8V ±5%
CML & Bidirectional Channel Driver Power, 1.8V ±5%
Digital Power, 1.8V ±5%
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from V
DDIO
.
V
DDIO
can be connected to a 1.8V ±5% or 2.8±10% or 3.3V ±10%
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
9 vias.
PDB
9
RES
7
FPD–Link III INTERFACE
DOUT+
DOUT-
POWER AND GROUND
VDDPLL
VDDT
VDDCML
VDDD
VDDIO
10
11
14
28
25
13
12
4
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Product Folder Links:
DS90UB913Q DS90UB914Q
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SNLS420B – JULY 2012 – REVISED APRIL 2013
VDDCML1
VDDIO1
GPIO[0]
VDDR
RIN1+
IDx[0]
36
35
34
33
32
31
30
PDB
29
28
27
GPIO[1]
IDx[1]
26
GPIO[2]
RIN1-
25
GPIO[3]
MODE
CMLOUTP
CMLOUTN
VDDCML0
RIN0+
RIN0-
RES
RES
VDDPLL
SEL
PASS
LOCK
37
38
39
40
41
42
43
44
45
46
47
48
10
11
12
1
2
3
4
5
6
7
8
9
24
ROUT[0]
ROUT[1]
ROUT[2]
ROUT[3]
VDDIO2
ROUT[4]
ROUT[5]
VDDD
ROUT[6]
ROUT[7]
ROUT[8]
ROUT[9]
DAP = GND
23
22
21
20
DS90UB914Q
48-Pin WQFN
(Top View)
19
18
17
16
15
14
13
ROUT[11]
VDDSSCG
OSS_SEL
Deserializer - DS90UB914Q — Top View
DS90UB914Q Deserializer Pin Descriptions
Pin Name
ROUT[11:0]
Pin No.
11,12,13,14,
15,16,18,19,
21,22,23,24
10
9
8
I/O, Type
Outputs,
LVCMOS
Output,
LVCMOS
Output,
LVCMOS
Output,
LVCMOS
Parallel Data Outputs.
Description
LVCMOS PARALLEL INTERFACE
HSYNC
VSYNC
PCLK
Horizontal SYNC Output.
Vertical SYNC Output.
Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
General-purpose input/output pins can be used to control and respond to various
commands. They may be configured to be the input signals for the corresponding
GPOs on the serializer or they may be configured to be outputs to follow local register
settings.
General purpose input/output pins GPO[2:3] can be configured to be input signals for
GPOs on the Serializer. In addition they can also be configured to be outputs to follow
the local register settings. When the SerDes chipsets are working with an external
oscillator, these pins can be configured only to be outputs to follow the local register
settings.
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to V
DDIO
.
Data line for bidirectional control bus communication
SDA requires an external pull-up resistor to V
DDIO
.
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
GPI0[1:0]
27,28
Digital
Input/Output,
LVCMOS
Digital
Input/Output
LVCMOS
GPIO[3:2]
25,26
BIDIRECTIONAL CONTROL BUS - I
2
C COMPATIBLE
SCL
SDA
2
1
Input/Output,
Open Drain
Input/Output,
Open Drain
ROUT[10]
PCLK
SDA
SCL
VSYNC
BISTEN
VDDIO3
HSYNC
OEN
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