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DS92001 3.3V B/LVDS-BLVDS Buffer

September 2006

DS92001

3.3V B/LVDS-BLVDS Buffer

General Description

The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input

signal and provides an BLVDS output signal. In many large

systems, signals are distributed across backplanes, and one

of the limiting factors for system speed is the "stub length" or

the distance between the transmission line and the untermi-

nated receivers on individual cards. Although it is generally

recognized that this distance should be as short as possible

to maximize system performance, real-world packaging con-

cerns often make it difficult to make the stubs as short as the

designer would like.

The DS92001 has edge transitions optimized for multidrop

backplanes where the switching frequency is in the 200 MHz

range or less. The output edge rate is critical in some sys-

tems where long stubs may be present, and utilizing a slow

transition allows for longer stub lengths.

The DS92001, available in the LLP (Leadless Leadframe

Package) package, will allow the receiver inputs to be placed

very close to the main transmission line, thus improving

system performance.

A wide input dynamic range allows the DS92001 to receive

differential signals from LVPECL as well as LVDS sources.

This will allow the device to also fill the role of an LVPECL-

BLVDS translator.

The LOS pin detects a non-driven B/LVDS bus state at the

input and provides an active LOW output. The LOS pin can

be tied to the device’s output enable pin (EN) to generate a

TRI-STATE output state when the input is un-driven. The

LOS pin can also be used locally to inform the system of the

bus state.

Features

Single +3.3 V Supply

B/LVDS receiver inputs accept LVPECL signals

TRI-STATE outputs

Loss of Signal (LOS) pin detects a non-driven bus

Receiver input threshold

100 mV

Fast propagation delay of 1.4 ns (typ)

Low jitter 400 Mbps fully differential data path

Compatible with BLVDS 10-bit SerDes (40MHz)

Compatible with ANSI/TIA/EIA-644-A LVDS standard

Available in SOIC and space saving LLP package

Industrial Temperature Range

Connection and Block Diagrams

SOIC - Top View

20024702

20024705

Functional Operation

BLVDS Inputs

[IN+] − [IN−]

VID

≥

0.1V

VID

≤

−0.1V

Full Fail-safe

OPEN/SHORTor Terminated

BLVDS Outputs

OUT+

OUT−

LLP - Top View

Ordering Information

20024743

Order Number

DS92001TMA

DS92001TLD

NS Pkg. No.

M08A

LDA08A

Pkg. Type

SOIC

LLP

DS200247

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DS92001

Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

)

LVCMOS/LVTTL Input Voltage

(EN)

LVCMOS/LVTTL Output Voltage

(LOS)

B/LVDS Receiver Input Voltage

(IN+, IN−)

BLVDS Driver Output Voltage

(OUT+, OUT−)

BLVDS Output Short Circuit

Current

Junction Temperature

Storage Temperature Range

Lead Temperature Range

Soldering (4 sec.)

+260˚C

−0.3V to +4V

−0.3V to (V

+ 0.3V)

−0.3V to (V

+ 0.3V)

Maximum Package Power Dissipation at 25˚C

M Package

Derate M Package

LDA Package

Derate LDA Package

ESD Ratings

(HBM, 1.5kΩ, 100pF)

(EIAJ, 0Ω, 200pF)

−0.3V to +4V

Continuous

+150˚C

−65˚C to +150˚C

≥2.5kV

≥250V

726 mW

5.8 mW/˚C above +25˚C

2.44 W

19.49 mW/˚C above

+25˚C

Recommended Operating

Conditions

Min

Supply Voltage (V

)

Receiver Differential Input

Voltage (V

) with

=1.2V

Operating Free Air

Temperature

B/LVDS Input Rise/Fall

20% to 80%

3.0

0.1

Typ

3.3

Max

3.6

2.4

Units

|V|

−40

+25

+85

˚C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)

Symbol

OSHLOS

Parameter

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Clamp Voltage

Output High Voltage

Output Low Voltage

(Note 5)

Output Short Circuit Current

(output high)(Note 4)

Differential Output Voltage

(Note 2)

Change in Magnitude of V

for Complimentary Output

States

Offset Voltage

Change in Magnitude of V

for Complimentary Output

States

Output TRI-STATE Current

Power-Off Leakage Current

= V

or 2.0V

= GND or 0.8V

= −18 mA

= −4mA, V

≥

|200mV|, V

= 1.2V

= 4mA, V

= 0V, V

= 1.2V

OUT

= 0V, 200mV

≤

2V, V

= 1.5V

−0.4V

−10

Conditions

Min

2.0

GND

Typ

Max

0.8

+20

+10

−1.5

0.4

−60

Units

µA

LVCMOS/LVTTL DC SPECIFICATIONS (EN)

−0.6

3.1

0.15

−35

LVCMOS/LVTTL DC SPECIFICATIONS (LOS)

BLVDS OUTPUT DC SPECIFICATIONS (OUT)

∆V

= 27Ω

= 50Ω

RL = 27Ω or 50Ω

Figure 1, Figure 2

= 27Ω or R

= 50Ω

Figure 1

EN = 0V, V

OUT

= V

or GND

= 0V or Open Circuit, V

OUT

= 3.6V

−20

+20

µA

1.1

1.25

1.375

250

350

450

500

600

∆V

OFF

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DS92001

Electrical Characteristics

Symbol

OS1

Parameter

Output Short Circuit Current

(Note 4)

(Continued)

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)

Conditions

EN = V

, V

= 1.2V,V

= 200mV, V

OUT+

= 0V,

= −200mV, V

= 1.2V, V

OUT−

= 0V

= −200mV, V

= 1.2V, V

OUT+

= V

, or

= 200mV, V

=1.2V, V

OUT−

= V

Min

Typ

Max

Units

BLVDS OUTPUT DC SPECIFICATIONS (OUT)

−30

−60

OSD

Differential Output Short Circuit

Current (Note 4)

EN = V

, V

= |200mV|, V

. = 1.2V, V

= 0V

(connect true and complement outputs through a

current meter)

= +0.05V, +1.2V or +3.25V

−70

|/2

= V

= 0V

= V

= 0V

Inputs open,

shorted, or

terminated

= 27Ω

= 50Ω

250

350

= 3.6V or 0V

|30|

|42|

B/LVDS RECEIVER DC SPECIFICATIONS (IN)

CMR

∆I

FSOD

Differential Input High

Threshold (Note 5)

Differential Input Low

Threshold (Note 5)

Common Mode Voltage Range

(Note 5)

Input Current

Change in Magnitude of I

Fail-safe BLVDS Outputs

(OUT+ is a more positive

voltage than OUT−)

(Note 5)

Total Dynamic Supply Current

(includes load current)

TRI-STATE Supply Current

−30

−|V

|/2

|1.5|

350

450

|20|

500

600

−5

µA

SUPPLY CURRENT

CCD

EN = V

, R

= 27Ω or 50Ω, C

= 15 pF,

Freq. = 200MHz 50% duty cycle,

= 200mV, V

= 1.2V

EN = 0V,Freq. = 200MHz 50% duty cycle,

= 200mV, V

= 1.2V

CCZ

AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3)

Symbol

PHLD

Parameter

Differential Propagation Delay

High to Low

(Note 10)

Differential Propagation Delay

Low to High

(Note 10)

Pulse Skew |t

PLHD

− t

PHLD

(measure of duty cycle)

(Notes 5, 6)

Part-to-Part Skew (Note 5)

(Note 7)

Part-to-Part Skew (Note 5)

(Note 8)

Rise Time (Notes 5, 10)

20% to 80% points

= 50Ω or 27Ω, C

= 15pF

Figure 3

and

Figure 5

Conditions

= 200mV, V

= 1.2V,

= 27Ω or 50Ω, C

= 15pF

Figure 3

and

Figure 4

Min

1.0

Typ

1.4

Max

2.0

Units

LVDS OUTPUT AC SPECIFICATIONS (OUT)

PLHD

1.0

1.4

2.0

SKD1

200

SKD3

SKD4

LHT

0.350

200

300

0.6

1.0

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DS92001

AC Electrical Characteristics

Symbol

HLT

PHZ

PLZ

PZH

PZL

MAX

Parameter

Fall Time (Notes 5, 10)

80% to 20% points

LVDS OUTPUT AC SPECIFICATIONS (OUT)

(Continued)

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3)

Conditions

Min

0.350

Typ

0.6

100

Max

1.0

120

Units

Disable Time (Active High to Z) R

= 50Ω, C

= 15pF

Disable Time (Active Low to Z)

Enable Time (Z to Active High)

Enable Time (Z to Active Low)

LVDS Data Jitter, Deterministic V

= 300mV; PRBS = 2

(Peak-to-Peak) (Note 9)

400Mbps (NRZ)

LVDS Clock Jitter, Random

(Note 9)

Maximum guaranteed

frequency

(Note 11)

− 1 data; V

= 1.2V at

Figure 6

and

Figure 7

= 300mV; V

= 1.2V at 200MHz clock

= 200mV, V

= 1.2V

200

300

MHz

LVCMOS/LVTTL AC SPECIFICATIONS (LOS)

PHLLOS

PLHLOS

LHLOS

HLLOS

LVTTL Propagation Delay High CL = 10pF, IN− = 1V, 1V

≤

IN+

≤

1.3V,

to Low (Note 5)

Freq. = 10MHz, 50% Duty Cycle

LVTTL Propagation Delay Low

Figures 8, 9

to High (Note 5)

Rise Time

20% to 80% (Note 5)

Fall Time

80% to 20% (Note 5)

1.3

Note 1:

“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device

should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2:

Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V

, V

, and

∆V

. V

has a value and direction. Positive direction means OUT+ is a more positive voltage than OUT−.

Note 3:

All typical are given for V

= +3.3V and T

= +25˚C, unless otherwise stated.

Note 4:

Output short circuit current (I

) is specified as magnitude only, minus sign indicates direction only.

Note 5:

The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT (process, voltage and

temperature) range.

Note 6:

SKD1

, |t

PLHD

− t

PHLD

|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of

the same channel (a measure of duty cycle).

Note 7:

SKD3

, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification

applies to devices at the same V

and within 5˚C of each other within the operating temperature range. This parameter guaranteed by design and characterization.

Note 8:

SKD4

, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices over recommended

operating temperature and voltage ranges, and across process distribution. t

SKD4

is defined as |Max − Min| differential propagation delay.

Note 9:

The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT range with the following test

equipment setup: Agilent 86130A used as stimulus, 5 feet of RG142B cable with DUT test board and Agilent 86100A (digital scope mainframe) with Agilent 86122A

(20GHz scope module). Data input jitter pk to pk = 22 picoseconds; Clock input jitter = 24 picoseconds; t

measured 100 picoseconds, t

measured 60

picoseconds.

Note 10:

Propagation delay, rise and fall times are guaranteed by design and characterization to 200MHz. Generator for these tests: 50MHz

≤

200MHz, Zo =

50Ω, tr, tf

≤

0.5ns. Generator used was HP8130A (300MHz capability).

Note 11:

MAX

test: Generator (HP8133A or equivalent), Input duty cycle = 50%. Output criteria: VOD

≥

200mV, Duty Cycle better than 45/55%. This specification

is guaranteed by design and characterization. A minimum is specified, which means that the device will operate to specified conditions from DC to the minimum

guaranteed AC frequency. The typical value is always greater than the minimum guarantee.

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DS92001

DC Test Circuits

20024703

FIGURE 1. Differential Driver DC Test Circuit

20024708

FIGURE 2. Differential Driver Full Load DC Test Circuit

AC Test Circuits and Timing Diagrams

20024706

FIGURE 3. BLVDS Output Load

20024707

FIGURE 4. Propagation Delay Low-to-High and High-to-Low

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