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DSC-11520

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16-BIT PIN PROGRAMMABLE

D/S OR D/R CONVERTER

FEATURES

•

Complete D/S or D/R Converter

•

Accuracy up to ± 1 Minute

•

DC-Coupled Reference - Accepts

Most Waveforms

•

Generates SIN/COS DC or Rotating

PPI Sweep

•

High-Rel CMOS D/R Chip

•

8-Bit/16-Bit Double-Buffered

Transparent Latches

DESCRIPTION

The DSC-11520 is a versatile multiplying Digital-to-Synchro/Resolver con-

verter. The digital input represents an angle and the output is pin program-

mable for either resolver type SIN/COS or three-line synchro output. The

device will accept most of the commonly used waveshapes as reference,

even a sawtooth input in the case of a CRT drive application. Because the

reference is DC-coupled to the output, the DSC-11520 can be used in many

configurations:

• Digital-to-Synchro or Digital-to-Resolver converter (using a sinusoidal

reference input)

• Hybrid Digital-to-SIN/COS DC converter (using a DC reference input)

• Polar to rectangular coordinates converter (using a reference input

proportional to the radius vector)

• Generate a cartwheel rotating sweep for PPI displays (using a saw-

tooth reference input and a rotating digital input)

Packaged in a 36-pin double DIP, the DSC-11520 is a complete D/S and D/R

converter in one hybrid module.

The DSC-11520 is a light, low power, very highly reliable device with a wide

operating temperature range. The internal hybrid circuit design results in high

accuracy and reduces the output scale factor so that the output can drive

displays directly. The output line-to-line voltage can be scaled by external

resistors. The reference input provides high AC and DC common mode rejec-

tion.

APPLICATIONS

The DSC-11520's high reliability, small size, and low power consumption

make it an ideal solution for most stringent and sever applications (industrial,

military ground vehicles, aircraft avionics, etc.). Among the many other pos-

sible applications are computer based systems in which digital information is

processed, such as simulators, flight trainers, flight instrumenation, fire con-

trol systems, radar and navigation systems, and PPI displays including mov-

ing target indicators. All versions of the DSC-11520 are available with MIL-

PRF-38534 processing as a standard ordering option.

FOR MORE INFORMATION CONTACT:

Data Device Corporation

105 Wilbur Place

Bohemia, New York 11716

631-567-5600 Fax: 631-567-7358

www.ddc-web.com

Technical Support:

1-800-DDC-5757 ext. 7771

All trademarks are the property of their respective owners.

1985, 1999 Data Device Corporation

Data Device Corporation

www.ddc-web.com

TEST POINT - R

D/R CONVERTER

REFERENCE

CONDITIONER

BITS 1-16

TRANSPARENT LATCH

S2'

S3'

HIGH ACCURACY

LOW SCALE FACTOR

VARIATION

ELECTRONC

SCOTT-T OR

RESOLVER

SCALING

OUTPUT

AMPLIFIERS

SYNCHRO

OR RESOLVER

OUTPUT

(PIN JUMPER

PROGRAMMABLE)

LA LM

BITS 1-8

BITS 9-16

DIGITAL INPUT

REF

INPUTS

26 V

100 kΩ

RH'

5 kΩ

ADJUSTABLE

1.3-26 V

RL'

5 kΩ

DSC-11520

P-06/09-0

FIGURE 1. DSC-11520 BLOCK DIAGRAM

TABLE 1. DSC-11520 SPECIFICATIONS

Apply over temperature range, power supply ranges, reference voltage

and frequency range and 10% harmonic distortion in the reference.

PARAMETER

RESOLUTION

ACCURACY AND

DYNAMICS

Output Accuracy

Differential Linearity

Output Settling Time

DIGITAL INPUT

Logic Type

16 bits

VALUE

POwER SUPPLY CYCLING

Power supply cycling of the DDC converter should follow the

guidelines below to avoid any potential problems. Strictly main-

tain proper sequencing of supplies and signals per typical CMOS

circuit guidelines:

1. Apply power supplies (+15V, -15V and ground)

2. Apply digital control signals

3. Apply analog signals

The reverse sequence should be followed during power down of

the circuit.

±8 minutes to ±1 min. (See Ordering Info.)

±1 LSB max

Less than 20 µsec for any digital step change.

Natural binary angle parallel positive logic CMOS and

TTL compatible.

Inputs are CMOS transient protected. Each input has

a 20 µA max pull down to GND.

V = +4.5 V to +15 V supply

Logic 0 = 0 to +0.8 V

Logic 1 = 2 V to 1/3 of VDD +10%

20 µA max (bit 1-16)

65 µA (LL, LM, LA) See Timing Diagram

(FIGURE 2)

Two differential solid-state inputs, one for standard

26 V input and one programmable.

DC to 1000 Hz

Standard Input

Programmable input

26 V ±10%

1.3 V min for full output;

higher voltages are scaled by

adding two series resistors

100 kΩ ± 0.5%

200 kΩ ± 0.5%

5 kΩ ± 0.5%

10 kΩ ± 0.5%

Logic Voltage Level

Load Current

OUTPUT SCALING AND REF. LEVEL ADJUSTMENT

The DSC-11520 operates like a multiplying D/A converter in that

the voltage of each output line is directly proportional to the refer-

ence voltage.

The maximum line-to-line levels are determined by the output

amplifiers and are nominally 11.8 Vrms for synchro output and

6.81 Vrms for resolver output.The RH, RL set of reference inputs

are designed to provide this nominal output for the standard 26

Vrms reference level. The scaling adjustment is made by two

internal 100 kΩ resistors in series with the reference conditioner

input (see Figure 1). The maximum output levels without distor-

tion are 10% greater than the nominal 11.8 Vrms and 6.81 V rms

levels.

The RH', RL' reference inputs have 5 kΩ internal resistors in

series with the reference conditioner input, so that nominal line-

to-line output is obtained for a reference input of 1.3 Vrms. For

higher reference voltages, two resistors R' must be inserted in

series with the inputs as shown in FIGURE 2. These resistors

scale the DSC-11520 outputs to the nominal 11.8 Vrms and 6.81

Vrms levels stated above, or to lower voltages if desired. The

magnitude of the resistors R' in ohms is calculated as follows:

R' = 5000 (VR - 1.3)

1.3

L-L VOLTAGE LEVEL

(

NOMINAL L-L VOLTAGE LEVEL

)

DESIRED

REFERENCE INPUT

Type

Frequency Range

Voltage

Input Impedance

Single Ended

Differential

ANALOG OUTPUT

Type

Output current

Max Output Voltage (Tracks

Reference Input Voltage)

Transformation Ratio Tol. +

Scale Factor Variation

DC Offset Each Line to

GND

POWER SUPPLIES

Voltage

Voltage Limits

Max Voltage Without

Damage

Current or impedance

Pin programmable for synchro or resolver mode.

2 mA rms max.

11.8 V rms L-L ±0.25%nominal in synchro mode

6.81 V rms L-L ±0.25%nominal resolver mode

±0.6% max

±15 mV standard, varies with input angle

±5 mV available- Consult Factory

+15 V

±5%

+18 V

-15 V

±5%

-18 V

20 mA max

No Vl required; +5 V logic levels are derived

internally.

TEMPERATURE RANGES

(CASE)

Operating

-1 Option

-3 Option

Storage

PHYSICAL

CHARACTERISTICS

Type

Size

Weight

OUTPUT PHASING AND OUTPUT SCALE FACTOR

The analog output signals have the following phasing:

Synchro output

S1 — S3 = (RH-RL) Ao (1 + A(θ)) sin

S3 — S2 = (RH-RL) Ao (1 + A(θ)) sin (θ + 120°)

S2 — S1 = (RH-RL) Ao (1 + A(θ)) sin (θ + 240°)

Resolver output

S1 — S3 = (RH-RL) Ao (1 + A(θ)) sin

S2 — S4 = (RH-RL) Ao (1 + A(θ)) cos

The output amplitudes simultaneously track reference voltage

fluctuations because they are proportional to (RH-RL). The trans-

formation ratio Ao is 11.8/26 for 11.8 V rms L-L output. The term

A (θ) represents the variation of the amplitude with the digital

input angle. A (θ), which is called the scale factor variation, is a

smooth function of

without discontinuities.

Because the amplitude factor (RH-RL) Ao (1 + A(θ)) varies simul-

taneously on all output lines, it will not be a source of error when

the DSC-11520 is to drive a ratiometric system such as a synchro

or resolver. However, if the outputs are used independently, as in

X-Y plotters, the amplitude variations must be taken into

account.

DSC-11520

P-06/09-0

-55°C to +125°C

0°C to +70°C

-55°C to 135°C

36-pin double DIP

0.78 X 1.9 X 0.21inch (2.0 X 4.8 X 0.53 cm)

0.85 oz (24g)

INTRODUCTION

As shown in Figure 1, the signal conversion in the DSC-11520 is

performed by a high accuracy Digital-to-Resolver converter

whose SIN and COS outputs have a low scale factor variation as

a function of the digital input angle. This resolver output is either

multiplied by scaling amplifiers for resolver output, or is both mul-

tiplied and converted to a synchro output by an electronic Scott-T.

The output line currents are limited to 2 mA rms max, which is

sufficient for driving S/D converters, solid-state control transform-

ers, and displays. Output power amplifiers will be required for

driving electro-mechanical devices such as synchros and resolv-

ers.

Data Device Corporation

www.ddc-web.com

REF

INPUT

RH'

DSC-11520

RL'

FIGURE 2. REFERENCE LEVEL ADJUSTMENT

200 ns min.

TRANSPARENT

LATCHED

DATA 1-16 BITS

125 ns min.

With LA set low =125 ns min.

With LL, LM, LA tied together = 200 ns min.

Data Changing

Data Stable

FIGURE 3A. LL, LM, LA TIMING DIAGRAM (16-BIT)

200 ns min.

200 ns

Bits (1-8)

200 ns min.

Bits (9-16)

DATA

125 ns min.

LA, LM, LL

Transparent = Hi

Latched = Lo

Data Changing

Data Stable

FIGURE 3B. LL, LM, LA TIMING DIAGRAM (8-BIT)

Data Device Corporation

www.ddc-web.com

DSC-11520

P-06/09-0

TABLE 2. PIN CONNECTIONS

FUNCTION

+15 V

GND

-15 V

-R

RL'

RH'

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1 (MSB)

Bit 15

Bit 16 (LSB)

S2'

S3'

S3 (+SIN)

S2 (+COS)

No Connect (no internal wire connection)

+15 VDC power supply voltage

Ground

-15 VDC power supply voltage

No Connect (no internal wire connection)

Test point used to detect whether a reference signal is present (see Figure 1). A signal between 6 V rms and 7.5 V rms

indicates that a reference input signal is present.

Reference input Lo (respective to RH)

Reference input Lo' (respective to RH')

Reference input Hi. Provides the maximum synchro or resolver output voltage for a standard 26 V rms reference input.

Reference input Hi'. Can be used to scale the output for other reference voltage levels. Series resistors can be added to the

reference input either to accomodate lower reference levels for full output, or to reduce the output level.

Angle data word Bit 14

Angle data word Bit 13

Angle data word Bit 12

Angle data word Bit 11

Angle data word Bit 10

Angle data word Bit 9

Angle data word Bit 8

Angle data word Bit 7

Angle data word Bit 6

Angle data word Bit 5

Angle data word Bit 4

Angle data word Bit 3

Angle data word Bit 2

Angle data word Bit 1 (MSB)

Angle data word Bit 15

Angle data word Bit 16 (LSB)

Active low control signal for latching angle data word bits 1 - 8. May be left unconnected when not used. (See Figure 3B for

timing diagrams).

Active low control signal for latching angle data word bits 9 - 16. May be left unconnected when not used. (See Figure 3B for

timing diagrams).

Active low control signal for latching angle data word bits 1 - 16. May be left unconnected when not used. (See Figure 3B for

timing diagrams).

No Connect (no internal wire connection)

Pin jumper programmable for synchro or single-ended resolver output. (see Figure 4)

DESCRIPTION

Data Device Corporation

www.ddc-web.com

DSC-11520

P-06/09-0