DSC400
Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
General Description
The DSC400 is a four output crystal-less™
clock generator. It utilizes Micrel’s proven
PureSilicon™ MEMS technology to provide
excellent
jitter
and
stability
while
incorporating additional device functionality.
The frequencies of the outputs can be
identical or independently derived from
common PLLs.
Each
output
may
be
configured
independently to support a single ended
LVCMOS interface or a differential interface.
Differential options include LVPECL, LVDS, or
HCSL.
The DSC400 provides two independent select
lines for choosing between two sets of pre-
configured frequencies per bank. It also has
two OE pins to allow for enabling and
disabling outputs.
The DSC400 is packaged in a 20-pin QFN
(5mm x 3.2mm) and is available in extended
commercial and
industrial
temperature
grades.
Features
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±25ppm, ±50ppm
Wide Temperature Range
o
Ext. commercial: -20°C to 70°C
o
Industrial: -40°C to 85°C
High Supply Noise Rejection: -50 dBc
Four format configurable outputs:
o
LVPECL, LVDS, HCSL, LVCMOS
Available Pin-Selectable frequency table
o
1 pin per bank for 2 frequency sets
Wide Freq. Range:
o
2.3 MHz – 460 MHz
20 QFN Footprint (5mm x 3.2mm)
Excellent Shock & Vibration Immunity
o
Qualified to MIL-STD-883
High Reliability
o
20x better MTF than quartz based devices
Wide Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
AEC-Q100 Automotive Qualified
Block Diagram
Applications
Communications and Networks
Ethernet
o
1G, 10GBASE-T/KR/LR/SR, and FCoE
Storage Area Networks
o
SATA, SAS, Fibre Channel
Passive Optical Networks
o
EPON, 10G-EPON, GPON, 10G-PON
HD/SD/SDI Video & Surveillance
Automotive
Media and Video
Embedded and Industrial
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DSC400
Page 1
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
18
19
20
Pin
Name
OE1
NC
VSS
VSS
CLK0-
CLK0+
CLK1-
CLK1+
VDD2
FSB2
OE2
NC
VSS
VSS
CLK2-
CLK2+
CLK3-
CLK3+
VDD1
FSB1
Pin
Type
I
NA
Power
Power
O
O
O
O
Power
I
I
NA
Power
Power
O
O
O
O
Power
I
Description
Output Enable for Bank1 (CLK0 and CLK3); active high – See Table 1
Leave unconnected or connect to ground
Ground
Ground
Complement output of differential pair 0 (off when in LVCMOS format)
True output of differential pair 0 or LVCMOS output 0
Complement output of differential pair 1 (off when in LVCMOS format)
True output of differential pair 1 or LVCMOS output 1
Power Supply for Bank2 (CLK1 and CLK2)
Input for selecting pre-configured frequencies on Bank2 (CLK1 and CLK2)
Output Enable for Bank2 (CLK1 and CLK2); active high – See Table 1
Leave unconnected or connect to ground
Ground
Ground
Complement output of differential pair 2 (off when in LVCMOS format)
True output of differential pair 2 or LVCMOS output 2
Complement output of differential pair 3 (off when in LVCMOS format)
True output of differential pair 3 or LVCMOS output 3
Power Supply for Bank1 (CLK0 and CLK3)
Input for selecting pre-configured frequencies on Bank1 (CLK0 and CLK3)
Pin Diagram
20 QFN 5.0 × 3.2mm
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DSC400
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DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Operational Description
The DSC400 is a crystal-less™ clock generator. Unlike older clock generators in the industry, it
does not require an external crystal to operate; it relies on the integrated MEMS resonator that
interfaces with internal PLLs. This technology enhances performance and reliability by allowing
tighter frequency stability over a far wider temperature range. In addition, the higher resistance to
shock and vibration decreases the aging rate to allow for much improved product life in the system.
Inputs
There are 4 input signals in the device. Each has an internal (40kΩ) pull up to default the selection
to a high (1). Inputs can be controlled through hardware strapping method with a resistor to
ground to assert the input low (0). Inputs may also be controlled by other components’ GPIOs
In case more than one frequency set is desired, FSB1 and FSB2 are used for independently
selecting one of two sets per bank. FSB1 selects the pre-configured set on Bank1 (CLK0 and CLK3)
and FSB2 selects the pre-configured set on Bank2 (CLK1 and CLK2), as shown in table 2.
If there is a requirement to disable outputs, the inputs OE1 and OE2 are used in conjunction to
disable the banks of outputs. Outputs are disabled in tristate (Hi-Z) mode, see Table 1 below.
Table 1: Output Enable (OE) Selection Table
OE1
0
0
1
1
OE2
0
1
0
1
Bank1 (CLK0 & CLK3)
Hi-Z
Hi-Z
Running
Running
Bank2 (CLK1 & CLK2)
Hi-Z
Running
Hi-Z
Running
Outputs
The four outputs are grouped into two banks. Each bank is supplied by an independent VDD to
allow for optimized noise isolation between the two banks. Each bank provides two synchronous
outputs generated by a common PLL:
Bank1 is composed of outputs CLK0 and CLK3
Bank2 is composed of outputs CLK1 and CLK2
Each output maybe pre-configured independently to be one of the following formats: LVCMOS,
LVDS, LVPECL or HCSL. In case the output is configured to be the single ended LVCMOS, the
frequency is generated on the true output (CLKx+) and the complement output (CLKx-) is shut off
in a low state. Frequencies can be chosen from 2.3MHz to 460MHz for differential outputs and from
2.3MHz to 170MHz on LVCMOS outputs.
Power
VDD1 and VDD2 supply the power to banks 1 and 2 respectively. Each VDD may have different
supply voltage from the other as long as it is within the 2.25V to 3.6V range. Each VDD pin should
have a 0.1µF capacitor to filter high frequency noise. VSS is common to the entire device.
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DSC400
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DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Ordering
Information
(Example shown in red font)
DSC400-
4 3 2 1
Q
x x x x K E 1 T
4
T
T
CLK3 Output Format
0: off
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
CLK2 Output Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
CLK1 Output Format
0: off
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
CLK0 Output Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
Packing
T: Tape & Reel
Stability
1: ±50ppm
2: ±25ppm
Temp Range
E: -20ºC to 70ºC
I: -40ºC to 85º
Package
K: 20 QFN
Frequency Code
Qxxxx is assigned
by factory; see
Table2
Factory configuration code assignment of Qxxxx
The DSC400 is meant for customers to define their own frequency requirements at the four
available outputs. The Qxxxx number identifies these specific customer requirements and is
assigned by the factory.
Table 2: Example of how FSB1 and FSB2 are applied and the Qxxxx code assignment
Bank1
Outputs
CLK0
CLK3
Bank2
Outputs
CLK1
CLK2
FSB1
1 (default)
125 MHz
50 MHz
FSB2
1 (default)
156.25 MHz
156.25 MHz
0
100 MHz
100 MHz
0
150 MHz
25 MHz
Qxxxx number
Q0001
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DSC400
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DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
Condition
40sec max.
Note: 1000+ years of data retention on internal memory
Specifications
Parameter
Supply Voltage
1
(Unless specified otherwise: Ta =25° C, VDD = 3.3V)
Symbol
V
DD
I
DDcore
Δf
Δf
Y1
Δf
Y2+
t
SU
V
IH
V
IL
t
DA
t
EN
R
PU
OE(1:2) transition from 1 to 0
OE(1:2) transition from 0 to 1
All input pins have an internal pull-
up
40
OE(1:2) = 0
All outputs are disabled
All temp and VDD ranges
1 year @25°C
Year 2 and beyond @25°C
T=25°C
0.75xV
DD
-
Condition
Min.
2.25
Typ.
40
Max.
3.6
44
±25
±50
±5
<±1/yr
5
-
0.25xV
DD
5
20
Unit
V
mA
ppm
ppm
ppm
ms
V
ns
ns
kΩ
Supply Current – Core
2
Frequency Stability
Aging – first year
Aging – after first year
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
4
Pull-Up Resistor
Notes:
1. V
DD
pins should be filtered with a 0.1µF capacitor connected between V
DD
and V
SS
.
2. The addition of IDD
core
and IDD
io
provides total current consumption of the device
3. t
su
is time to 100 ppm stable output frequency after V
DD
is applied and outputs are enabled.
4. Output Waveform figures below the parameters. See Output Waveform section
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DSC400
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