DSC513-05
Crystal-less™ Four Output 200 MHz Clock Generator
General Description
The DSC513-05 is a Crystal-less™, four
output clock generator. The clock generator
uses proven silicon MEMS technology to
provide 200 MHz at each output with
excellent jitter and stability over a wide
range of supply voltages and temperatures.
By eliminating the external quartz crystal,
MEMS
clock
generators
significantly
enhance reliability and accelerate product
development, while meeting stringent clock
performance criteria for a variety of
communications, storage, and networking
applications.
DSC513-05 has input pins OE1 and OE2 for
Output Enable / Disable feature allowing it
to disable all outputs when OE(1:2) = 0.
Each output enable pin controls a bank of
two synchronous clocks.See the OE function
table 1 for more detail.
The device is available in a 20 pin QFN.
Output formats are available in any
combination of LVPECL, LVDS, HCSL and
LVCMOS
Features
Available Output Formats:
o
o
o
o
HCSL, LVPECL, LVDS or LVCMOS per output
Ext. Industrial: -40° to 105° C
Industrial: -40° to 85° C
Ext. commercial: -20° to 70° C
Wide Temperature Range
Supply Range of 2.25 to 3.6 V
Low Power Consumption
o
o
o
30% lower than competing devices
Qualified to MIL-STD-883
20 QFN, 5mm x 3.2mm
Excellent Shock & Vibration Immunity
Package:
Lead Free & RoHS Compliant
Short Lead Time: 2 Weeks
AEC-Q100 Automotive Qualified
Block Diagram
Applications
Communications/Networking
o
o
o
o
o
Ethernet
1G, 10GBASE-T/KR/LR/SR, and FcoE
Routers and Switches
Gateways, VoIP, Wireless AP’s
Passive Optical Networks
Embedded Applications
*
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DSC513-05
Page 1
Clk0+/-, Clk1+/-, Clk2 +/- and Clk3 +/- are
200 MHz. For other frequencies,
please contact the factory.
DSC513-05
Crystal-less ™ Four Output 200 MHz Clock Generator
Specifications
(Unless specified otherwise: T=25° C,
VDD =3.3V)
Parameter
Supply Voltage
1
Frequency Stability
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
V
DD
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up on OE pin
40
Includes frequency variations
due to initial tolerance, temp.
and power supply voltage
T=25°C
0.75xV
DD
-
Condition
Min.
2.25
Typ.
Max.
3.6
±100
±50
5
-
0.25xV
DD
5
20
Unit
V
ppm
ms
V
ns
ns
kΩ
Parameter
Condition
LVDS Outputs
All outputs running at 200MHz,
R
L
=100Ω
All outputs disabled
R
L
=100Ω Differential
Single-Ended
20% to 80%
R
L
=100Ω, C
L
= 2pF
At any output
Differential
200kHz to 20MHz @ 200 MHz
100kHz to 20MHz @ 200 MHz
12kHz to 20MHz @ 200 MHz
Min.
Typ.
110
29
Max.
TBD
TBD
1.4
50
Unit
Supply Current
2
(All LVDS outputs)
Output offset Voltage
Delta Offset Voltage
Pk to Pk Output Swing
Output Transition time
3
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
Integrated Phase Noise
Notes:
1.
2.
3.
4.
I
DD
V
OS
∆V
OS
mA
V
mV
mV
1.125
350
200
2.3
48
2.5
V
PP
t
R
t
F
f
0
SYM
J
PER
J
PH
TBD
460
52
TBD
TBD
2
ps
MHz
%
ps
RMS
ps
RMS
1.7
VDD pins 9 and 19 should be filtered with 0.1uf capacitor.
t
su
is setup time to achieve 100ppm at output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Output is enabled if OE pin is floated or not connected.
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DSC513-05
Page 2
DSC513-05
Crystal-less ™ Four Output 200 MHz Clock Generator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
Condition
40sec max.
Solder Reflow Profile
20-40
Sec
Temperature (°C)
217
°
C
200
°
C
.
ax
3C
/
Se
cM
ax
60-150
Sec
260
°
C
.
S
6C/
6C/
6C/
c
c
ec
Ma
Ma
Ma
150
°
C
3C
/
Se
60-180
Sec
cM
Reflow
.
.
x.
Pre heat
8 min max
Cool
Time
25
°
C
20 QFN
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
3°C/Sec Max.
Preheat Time 150°C to 200°C
60-180 Sec
Time maintained above 217°C
60-150 Sec
Peak Temperature
255-260°C
Time within 5°C of actual Peak
20-40 Sec
Ramp-Down Rate
6°C/Sec Max.
Time 25°C to Peak Temperature
8 min Max.
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DSC513-05
Page 3
DSC513-05
Crystal-less ™ Four Output 200 MHz Clock Generator
Pin Description (20 QFN)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
OE1
NC
VSS
VSS
CLK0-
CLK0+
CLK1-
CLK1+
VDD
NC
OE2
NC
VSS
VSS
CLK2-
CLK2+
CLK3-
CLK3+
VDD
NC
Pin Type
I
NA
Power
Power
O
O
O
O
Power
NA
I
NA
Power
Power
O
O
O
O
Power
NA
Description
Output Enable; active high
Leave unconnected or grounded
Ground
Ground
Complement output of differential pair (200MHz)
True output of differential pair (200MHz)
Complement output of differential pair (200MHz)
True output of differential pair (200MHz)
Power Supply
Leave unconnected or grounded
Output Enable; active high
Leave unconnected or grounded
Ground
Ground
Complement output of differential pair (200MHz)
True output of differential pair (200MHz)
Complement output of differential pair (200MHz)
True output of differential pair (200MHz)
Power Supply
Leave unconnected or grounded
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DSC513-05
Page 4
DSC513-05
Crystal-less ™ Four Output 200 MHz Clock Generator
Pin Diagram (20
QFN)
CLK3+
CLK2+
CLK3-
20
OE1
NC
VSS
VSS
1
2
3
4
5
CLK0-
19
18
17
16
15
14
13
12
11
VSS
VSS
NC
OE2
6
CLK0+
7
CLK1-
8
CLK1+
9
VDD
10
NC
20 QFN 5.0 x 3.2mm
Connection Diagram (20 QFN, Four LVDS Outputs)
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DSC513-05
Page 5
CLK2-
VDD
NC
stm32/stm8
