DSC557-05
Crystal-less™ Four Output PCIe Clock Generator
General Description
The DSC557-05 is a Crystal-less™, four
output PCI express clock generator meeting
Gen1, Gen2, and Gen3 specifications. The
clock generator uses proven silicon MEMS
technology to provide excellent jitter and
stability over a wide range of supply
voltages and temperatures. By eliminating
the external quartz crystal, MEMS clock
generators significantly enhance reliability
and accelerate product development, while
meeting stringent clock performance criteria
for a variety of communications, storage,
and networking applications.
DSC557-05 has an Output Enable / Disable
feature allowing it to disable all outputs
when OE1 and OE2 are low. Each output
enable
pin
controls
two
banks
of
synchronous PCIe clocks.
See the OE
function diagram for more detail.
The
device is available in a 20 pin QFN.
Additional output formats are in any
combination of LVPECL, LVDS, and HCSL.
Features
Meets PCIe Gen1, Gen2 & Gen3 specs
Available Output Formats:
o
o
o
o
o
HCSL, LVPECL, or LVDS
Mixed Outputs: LVPECL/HCSL/LVDS
Ext. Industrial: -40° to 105° C
Industrial: -40° to 85° C
Ext. commercial: -20° to 70° C
Wide Temperature Range
Supply Range of 2.25 to 3.6 V
Low Power Consumption
o
o
o
30% lower than competing devices
Qualified to MIL-STD-883
20 QFN
Excellent Shock & Vibration Immunity
Available Footprints:
Lead Free & RoHS Compliant
Block Diagram
Applications
Communications/Networking
o
o
o
o
o
Ethernet
1G, 10GBASE-T/KR/LR/SR, and FcoE
Routers and Switches
Gateways, VoIP, Wireless AP’s
Passive Optical Networks
*
Clk0+/-, Clk1+/-, Clk2 +/- and Clk3 +/- are
100 MHz as per PCIe standards. For other
frequencies, please contact the factory.
Storage
o
SAN, NAS, SSD, JBOD
Embedded Applications
o
Industrial, Medical, and Avionics
o
Security Systems and Office
Automation
o
Digital Signage, POS and others
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DSC557-05
Page 1
Consumer Electronics
o
Smart TV, Bluray, STB
DSC557-05
Crystal-less Four Output PCIe Clock Generator
Specifications
(Unless specified otherwise: T=25° C,
VDD =3.3V)
Parameter
Supply Voltage
1
Supply Current
Supply Current
2
(Four HCSL Outputs)
V
DD
I
DD
I
DD
EN pin low – outputs are
disabled
EN pin high – outputs are
enabled
R
L
=50 Ω,
F
O1
=F
O2
=F
O3
= F
O4
=100 MHz
Includes frequency variations
due to initial tolerance, temp.
and power supply voltage
T=25°C
0.75xV
DD
-
Condition
Min.
2.25
Typ.
42
Max.
3.6
46
Unit
V
mA
120
±100
±50
5
-
0.25xV
DD
5
20
mA
Frequency Stability
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
ppm
ms
V
ns
ns
kΩ
Pull-up on OE pin
40
HCSL Outputs
6
Parameter
Output Logic Levels
Output logic high
Output logic low
Pk to Pk Output Swing
Output Transition time
4
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
t
R
t
F
f
0
SYM
J
PER
T
J
Jitter, Phase
(Common Clock
Architecture)
J
RMS-CCHF
J
RMS-CCLF
J
RMS-CC
Integrated Phase Noise
(Data Clock
Architecture)
J
RMS-DCHF
J
RMS-DCLF
J
RMS-DC
V
OH
V
OL
Condition
R
L
=50Ω
Single-Ended
20% to 80%
R
L
=50Ω, C
L
= 2pF
Single Frequency
Differential
F
O1
=F
O2
= F
O3
= F
O4
=100 MHz
PCIe Gen 1.1
PCIe Gen 2.1, 1.5MHz to Nyquist
PCIe Gen 2.1, 10 kHz to 1.5 MHz
PCIe Gen 3.0
PCIe Gen 2.1, 1.5MHz to Nyquist
PCIe Gen 2.1, 10 kHz to 1.5 MHz
PCIe Gen 3.0
Min.
0.725
-
Typ.
Max.
-
0.1
Unit
V
mV
750
200
2.3
48
2.5
22.7
2.20
0.08
0.37
2.15
0.06
0.32
86.0
8
3.1
8
3.0
8
1.0
8
4.0
8
7.5
8
1.0
8
100
7
400
460
52
ps
MHz
%
ps
RMS
ps
p-p
ps
RMS
ps
RMS
ps
RMS
ps
RMS
ps
RMS
ps
RMS
Notes:
1. Each V
DD
pin should be filtered with 0.01uf capacitor.
2. Output is enabled if OE pin is floated or not connected.
3. t
su
is time to 100PPM stable output frequency after V
DD
is applied and outputs are enabled.
4. Output Waveform and Connection Diagram define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
6. Contact
Sales@Discera.com
for alternate output options (LVPECL, LVDS, LVCMOS).
7. Contact
Sales@Discera.com
for alternative frequency options
8. Jitter limits established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards.
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DSC557-05
Page 2
DSC557-05
Crystal-less Four Output PCIe Clock Generator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
Condition
40sec max.
Solder Reflow Profile
20-40
Sec
Temperature (°C)
217
°
C
200
°
C
.
ax
3C
/
Se
cM
ax
60-150
Sec
260
°
C
.
S
6C/
6C/
6C/
c
c
ec
Ma
Ma
Ma
150
°
C
3C
/
Se
60-180
Sec
cM
Reflow
.
.
x.
Pre heat
8 min max
Cool
Time
25
°
C
20 QFN
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
3°C/Sec Max.
Preheat Time 150°C to 200°C
60-180 Sec
Time maintained above 217°C
60-150 Sec
Peak Temperature
255-260°C
Time within 5°C of actual Peak
20-40 Sec
Ramp-Down Rate
6°C/Sec Max.
Time 25°C to Peak Temperature
8 min Max.
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DSC557-05
Page 3
DSC557-05
Pin Description (20 QFN)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
OE1
NC
VSS
VSS
CLK0-
CLK0+
CLK1-
CLK1+
VDD
NC
OE2
NC
VSS
VSS
CLK2-
CLK2+
CLK3-
CLK3+
VDD
NC
Crystal-less Four Output PCIe Clock Generator
Pin Type
I
NA
Power
Power
O
O
O
O
Power
NA
I
NA
Power
Power
O
O
O
O
Power
NA
Description
Output Enable; active high
Leave unconnected or grounded
Ground
Ground
Complement output of differential
True output of differential pair
Complement output of differential
True output of differential pair
Power Supply
Leave unconnected or grounded
Output Enable; active high
Leave unconnected or grounded
Ground
Ground
Complement output of differential
True output of differential pair
Complement output of differential
True output of differential pair
Power Supply
Leave unconnected or grounded
pair
pair
pair
pair
Pin Diagram (20
QFN)
Connection Diagram
(20 QFN Four HCSL Outputs)
CLK3+
CLK2+
CLK3-
20
OE1
NC
VSS
VSS
1
2
3
4
5
CLK0-
19
18
17
16
15
14
13
12
11
VSS
VSS
NC
OE2
6
CLK0+
7
CLK1-
8
CLK1+
9
VDD
10
NC
20 QFN 5.0 x 3.2mm
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DSC557-05
Page 4
CLK2-
VDD
NC
DSC557-05
Crystal-less Four Output PCIe Clock Generator
OE Function and
Output Waveform: HCSL
t
R
CLK+
80%
50%
20%
CLK-
1/f
0
t
DA
t
EN
V
IH
675mV
t
F
OE
V
IL
CLK1/CLK2 Synchronous
OE1
0
0
1
1
OE2
0
1
0
1
CLK0
Hi-Z
Hi-Z
EN
EN
CLK1
Hi-Z
EN
Hi-Z
EN
CLK2
Hi-Z
EN
Hi-Z
EN
CLK3
Hi-Z
Hi-Z
EN
EN
CLK0/CLK3 Synchronous
Ordering
Information
DSC557-05
4 4 4 4 K I 0 T
4
T
4
CLK 3 Output Format
1: LVCMOS
4
2: LVPECL
4
3: LVDS
4
4: HCSL
4
CLK 2 Output Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
CLK 1 Output Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
CLK 0 Output Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
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DSC557-05
Page 5
Packing
T: Tape & Reel
Stability
0: ±100ppm
1: ±50ppm
Temp Range
E: -20 to 70
I: -40 to 85
L: -40 to 105
Package
K: 20 QFN
