DSC571-04
Crystal-less™ XAUI/SGMI/SRIO/PCIe Clock Generator
General Description
The DSC571-04 is a Crystal-less™ XAUI
clock generator with support for SGMI,
SRIO and PCI express Gen1, Gen2, and
Gen3 specifications. The clock generator
uses proven silicon MEMS technology to
provide excellent jitter and stability over a
wide range of supply voltages and
temperatures. By eliminating the external
quartz crystal, MEMS clock generators
significantly
enhance
reliability
and
accelerate product development, while
meeting stringent clock performance criteria
for a variety of communications, storage,
and networking applications.
DSC571-04 has input pins OE1 and OE2 for
Output Enable / Disable feature allowing it
to disable all outputs when OE(1:2) = 0.
See the OE function table 1 for more detail.
The device is available in a 20 pin QFN.
Output formats are available in any
combination of LVPECL, LVDS, HCSL and
LVCMOS
Features
Three outputs (typical format usage):
o
o
o
XAUI: 156.25MHz (LVPECL)
SGMI/SRIO: 125MHz (LVPECL)
PCIe: 100MHz (HCSL)
XAUI, SGMI, SRIO & PCIe Ready
Available Output Formats:
o
o
o
o
HCSL, LVPECL, LVDS or LVCMOS per output
Industrial: -40° to 85° C
Ext. commercial: -20° to 70° C
For additional temp ranges, contact factory
Wide Temperature Range
Supply Range of 2.25 to 3.6 V
Low Power Consumption
o
o
o
30% lower than competing devices
Qualified to MIL-STD-883
5.0mm x 3.2mm 20 QFN
Excellent Shock & Vibration Immunity
Available Footprints: 5.0 x 3.2mm
Lead Free & RoHS Compliant
Short Lead Time: 2 Weeks
AEC-Q100 Automotive Qualified
Block Diagram*
Control Circuitry
Output
Control
and
Divider
CLK0+
CLK0-
CLK1+
CLK1-
CLK2-
CLK2+
MEMS
PLLs
Applications
Communications/Networking
o
o
o
o
o
Ethernet
1G, 10GBASE-T/KR/LR/SR, and FcoE
Routers and Switches
Gateways, VoIP, Wireless AP’s
Passive Optical Networks
OE1
OE2
*
Clk0+/- is 100MHz per PCIe standard.
Clk1+/- is 125MHz per SGMI/SRIO requirements.
Clk2 +/- is 156.25MHz per XAUI standards.
For other frequencies, please contact the factory.
Storage
o
SAN, NAS, SSD, JBOD
Embedded Applications
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DSC571-04
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DSC571-04
Crystal-less™ XAUI/SGMI/SRIO/PCIe Clock Generator
Specifications
(Unless specified otherwise: T=25° C,
VDD =3.3V)
Parameter
Supply Voltage
1
Supply Current
Supply Current
2
Frequency Stability
Startup Time
3
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
Output logic high
Output logic low
Pk to Pk Output Swing
Output Transition time
4
Rise Time
Fall Time
Frequency
Output Duty Cycle
Integrated Phase Noise
t
R
t
F
f
0
SYM
J
PH
V
OH
V
OL
V
DD
I
DD
I
DD
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up on OE pin
40
V
DD
-1.08
-
800
250
2.3
48
0.2
1.7
460
52
2
-
V
DD
-1.55
EN pin low – outputs are disabled
All outputs are enabled, R
L
=50 Ω
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
T=25°C
0.75xV
DD
-
Condition
Min.
2.25
Typ.
42
100
Max.
3.6
46
Unit
V
mA
mA
±100
±50
5
-
0.25xV
DD
5
20
ppm
ms
V
ns
ns
kΩ
XAUI LVPECL Output (CLK2)
R
L
=50Ω
Single-Ended
20% to 80%
R
L
=50Ω, C
L
= 0pF (to GND)
Single Frequency
Differential
1.875MHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
V
mV
ps
MHz
%
ps
RMS
SGMII/SRIO LVPECL Output (CLK1)
Output logic high
Output logic low
Pk to Pk Output Swing
Output Transition time
Rise Time
Fall Time
Frequency
Output Duty Cycle
Jitter, Max Cycle to Cycle
4
V
OH
V
OL
R
L
=50Ω
Single-Ended
V
DD
-1.08
-
800
250
2.3
48
24
0.2
1.7
-
V
DD
-1.55
V
mV
ps
t
R
t
F
f
0
SYM
J
CC
20% to 80%
R
L
=50Ω, C
L
= 0pF (to GND)
Single Frequency
Differential
F = 125MHz
5
1.875MHz to 20MHz @125MHz
12kHz to 20MHz @125MHz
460
52
MHz
%
Ps
Integrated Phase Noise
J
PH
2
ps
RMS
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DSC571-04
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DSC571-04
Crystal-less™ XAUI/SGMI/SRIO/PCIe Clock Generator
PCIe HCSL Output (CLK0)
Parameter
Output logic high
Output logic low
Pk to Pk Output Swing
Output Transition time
1
Rise Time
Fall Time
Output Duty Cycle
Period Jitter
t
R
t
F
SYM
J
PER
R
J
D
J
T
J
J
RMS-CCHF
J
RMS-CCLF
J
RMS-CC
Integrated Phase Noise
(Data Clock
Architecture)
J
RMS-DCHF
J
RMS-DCLF
J
RMS-DC
V
OH
V
OL
Condition
R
L
=50Ω
Single-Ended
20% to 80%
R
L
=50Ω, C
L
= 2pF
Differential
F
O1
=F
O2
= F
O3
=100 MHz
PCIe Gen 1.1,
T
J
=D
J
+ 14.069 x R
J
(BER 10-12)
PCIe Gen 2.1, 1.5MHz to Nyquist
PCIe Gen 2.1, 10 kHz to 1.5 MHz
PCIe Gen 3.0
PCIe Gen 2.1, 1.5MHz to Nyquist
PCIe Gen 2.1, 10 kHz to 1.5 MHz
PCIe Gen 3.0
Min.
0.725
-
Typ.
Max.
-
0.1
Unit
V
mV
750
200
48
2.5
0.584
TBD
TBD
0.493
0.035
0.166
0.459
2.004
0.181
4.7
41.9
6
86.0
6
3.1
6
3.0
6
1.0
6
4.0
6
7.5
6
1.0
6
6
400
52
ps
%
ps
RMS
ps
p-p
ps
RMS
ps
RMS
ps
RMS
ps
RMS
ps
RMS
ps
RMS
Jitter, Phase
(Common Clock
Architecture)
Notes:
Notes:
1. Pin 4 V
DD
should be filtered with 0.01uf capacitor.
2. Output is enabled if Enable pad is floated or not connected.
3. t
su
is time to stable output frequency after V
DD
is applied and outputs are enabled.
4. Output Waveform and Test Circuit figures below define the parameters.
5. Measured over 50k cycles.
6. Jitter limits established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards.
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DSC571-04
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DSC571-04
Crystal-less™ XAUI/SGMI/SRIO/PCIe Clock Generator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
Condition
40sec max.
Solder Reflow Profile
20-40
Sec
Temperature (°C)
217
°
C
200
°
C
.
ax
3C
/
Se
cM
ax
60-150
Sec
260
°
C
.
S
6C/
6C/
6C/
c
c
ec
Ma
Ma
Ma
150
°
C
3C
/
Se
60-180
Sec
cM
Reflow
.
.
x.
Pre heat
8 min max
Cool
Time
25
°
C
20 QFN
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
3°C/Sec Max.
Preheat Time 150°C to 200°C
60-180 Sec
Time maintained above 217°C
60-150 Sec
Peak Temperature
255-260°C
Time within 5°C of actual Peak
20-40 Sec
Ramp-Down Rate
6°C/Sec Max.
Time 25°C to Peak Temperature
8 min Max.
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DSC571-04
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DSC571-04
Crystal-less™ XAUI/SGMI/SRIO/PCIe Clock Generator
Pin Description (20 QFN)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
OE1
NC
VSS
VSS
CLK0-
CLK0+
CLK1-
CLK1+
VDD
NC
OE2
NC
VSS
VSS
CLK2-
CLK2+
NC
NC
VDD
NC
Pin Type
I
NA
Power
Power
O
O
O
O
Power
NA
I
NA
Power
Power
O
O
NA
NA
Power
NA
Description
Output Enable; active high
Leave unconnected or grounded
Ground
Ground
Complement output of differential pair (100MHz)
True output of differential pair (100MHz)
Complement output of differential use (125MHz)
True output of differential pair (125MHz)
Power Supply
Leave unconnected or grounded
Output Enable; active high
Leave unconnected or grounded
Ground
Ground
Complement output of differential pair (156.25MHz)
True output of differential pair (156.25MHz)
Package pin is Not Connected to internal IC or MEMS
Package pin is Not Connected to internal IC or MEMS
Power Supply
Leave unconnected or grounded
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DSC571-04
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