dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X Family Silicon Errata and Data Sheet Clarification
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X family devices that you
have received conform functionally to the current Device
Data Sheet (DS70000657H), except for the anomalies
described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in
Table 1.
The silicon issues are summarized in
Table 2.
The errata described in this document will be
addressed in future revisions of dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. The current
silicon revision levels are:
dsPIC33/PIC24EP32:
A3, A8
dsPIC33/PIC24EP64:
A2, A3, A8
dsPIC33/PIC24EP128:
A3, A8
dsPIC33/PIC24EP256:
A3, A8, A9
dsPIC33/PIC24EP512:
A7
“N/A” indicates that the device family is
not released, or that the particular silicon
issue does not apply to this family.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 3 or
PICkit™ 3:
1.
Using the appropriate interface, connect the device
to the MPLAB ICD 3 programmer/debugger or
PICkit 3.
From the main menu in MPLAB IDE, select
Configure>Select Device,
and then select the
target part number in the dialog box.
Select
the
MPLAB
hardware
tool
(Debugger>Select
Tool).
Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the devel-
opment tool used, the part number
and
Device
Revision ID value appear in the
Output
window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
2.
3.
4.
The Device and Revision ID values for the various
silicon revisions are shown in
Table 1.
Data Sheet clarifications and corrections start on
Page 27,
following the discussion of silicon issues.
2011-2018 Microchip Technology Inc.
DS80000533N-page 1
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
TABLE 1:
SILICON DEVREV VALUES
Device ID
(1)
0x1C19
0x1C1A
0x1C18
0x1C0D
0x1C0E
0x1C0C
0x1C11
0x1C12
0x1C10
0x1C01
0x1C02
0x1C00
0x1C05
0x1C06
0x1C04
0x1D27
0x1D39
0x1D3A
0x1D38
0x1D3B
0x1D2D
0x1D2E
0x1D2C
0x1D2F
0x1D31
0x1D32
0x1D30
0x1D33
0x1D21
0x1D22
0x1D20
0x1D23
0x1D25
0x1D26
0x1D24
0x1D27
A2
0x4002
A3
0x4003
A8
0x4008
—
—
A3
0x4003
A8
0x4008
—
Silicon Revision/Device ID
(2)
Part Number
PIC24EP32GP202
PIC24EP32GP203
PIC24EP32GP204
dsPIC33EP32GP502
dsPIC33EP32GP503
dsPIC33EP32GP504
PIC24EP32MC202
PIC24EP32MC203
PIC24EP32MC204
dsPIC33EP32MC202
dsPIC33EP32MC203
dsPIC33EP32MC204
dsPIC33EP32MC502
dsPIC33EP32MC503
dsPIC33EP32MC504
dsPIC33EP32MC506
PIC24EP64GP202
PIC24EP64GP203
PIC24EP64GP204
PIC24EP64GP206
dsPIC33EP64GP502
dsPIC33EP64GP503
dsPIC33EP64GP504
dsPIC33EP64GP506
PIC24EP64MC202
PIC24EP64MC203
PIC24EP64MC204
PIC24EP64MC206
dsPIC33EP64MC202
dsPIC33EP64MC203
dsPIC33EP64MC204
dsPIC33EP64MC206
dsPIC33EP64MC502
dsPIC33EP64MC503
dsPIC33EP64MC504
dsPIC33EP64MC506
Note 1:
2:
The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
Refer to the
“dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration
Bits”
(DS70663) for detailed information on Device and Revision IDs for your specific device.
DS80000533N-page 2
2011-2018 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
TABLE 1:
SILICON DEVREV VALUES (CONTINUED)
Device ID
(1)
0x1E59
0x1E58
0x1E5B
0x1E4D
0x1E4C
0x1E4F
0x1E51
0x1E50
0x1E53
0x1E41
0x1E40
0x1E43
0x1E45
0x1E44
0x1E47
0x1F79
0x1F78
0x1F7B
0x1F6D
0x1F6C
0x1F6F
0x1F71
0x1F70
0x1F73
0x1F61
0x1F60
0x1F63
0x1F65
0x1F64
0x1F67
—
A3
0x4003
A8
0x4008
A9
0x4009
—
A3
0x4003
A8
0x4008
—
Silicon Revision/Device ID
(2)
Part Number
PIC24EP128GP202
PIC24EP128GP204
PIC24EP128GP206
dsPIC33EP128GP502
dsPIC33EP128GP504
dsPIC33EP128GP506
PIC24EP128MC202
PIC24EP128MC204
PIC24EP128MC206
dsPIC33EP128MC202
dsPIC33EP128MC204
dsPIC33EP128MC206
dsPIC33EP128MC502
dsPIC33EP128MC504
dsPIC33EP128MC506
PIC24EP256GP202
PIC24EP256GP204
PIC24EP256GP206
dsPIC33EP256GP502
dsPIC33EP256GP504
dsPIC33EP256GP506
PIC24EP256MC202
PIC24EP256MC204
PIC24EP256MC206
dsPIC33EP256MC202
dsPIC33EP256MC204
dsPIC33EP256MC206
dsPIC33EP256MC502
dsPIC33EP256MC504
dsPIC33EP256MC506
Note 1:
2:
The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
Refer to the
“dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration
Bits”
(DS70663) for detailed information on Device and Revision IDs for your specific device.
2011-2018 Microchip Technology Inc.
DS80000533N-page 3
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
TABLE 1:
SILICON DEVREV VALUES (CONTINUED)
Device ID
(1)
0x1799
0x1798
0x179B
0x178D
0x178C
0x178F
0x1791
0x1790
0x1793
0x1781
0x1780
0x1783
0x1785
0x1784
0x1787
—
A7
0x4007
—
—
Silicon Revision/Device ID
(2)
Part Number
PIC24EP512GP202
PIC24EP512GP204
PIC24EP512GP206
dsPIC33EP512GP502
dsPIC33EP512GP504
dsPIC33EP512GP506
PIC24EP512MC202
PIC24EP512MC204
PIC24EP512MC206
dsPIC33EP512MC202
dsPIC33EP512MC204
dsPIC33EP512MC206
dsPIC33EP512MC502
dsPIC33EP512MC504
dsPIC33EP512MC506
Note 1:
2:
The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
Refer to the
“dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration
Bits”
(DS70663) for detailed information on Device and Revision IDs for your specific device.
DS80000533N-page 4
2011-2018 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
TABLE 2:
Module
CPU
CPU
SPI
SPI
UART
Power System
ADC
PTG
Op Amp
SILICON ISSUE SUMMARY
Feature
div.sd
DO
Loop
Frame Sync Pulse
Frame Sync Pulse
TX Interrupt
Flash Regulator
DONE bit
Strobe Output
Enabling Op Amp
mode
AC/DC Electrical
Characteristics
Dead-Time
Compensation
Flash Programming
Index Counter
Modulo Mode
Master Time Base
Mode
Item
Number
1.
2.
3.
4.
5.
6.
7.
8.
9.
Issue Summary
When using the
div.sd
instruction, the Overflow bit is not getting
set when an overflow occurs.
PSV access, including Table Reads or Writes in the first or last
instruction of a
DO
loop, is not allowed.
Frame Sync pulse is not generated in Master mode when
FRMPOL =
0.
When in SPI Slave mode, with the Frame Sync pulse set as an
input, FRMDLY must be set to ‘0’.
A Transmit (TX) interrupt may occur before the data transmission is
complete.
The VREGSF (RCON<11>) bit always reads back as ‘0’.
The ADC Conversion Status bit (DONE) does not work when an
external interrupt is selected as the ADC trigger source.
Strobe output pulse width is incorrectly dependent on the
PTGPWD<3:0> (PTGCON<7:4>) bits setting.
When using any of these op amp modules, or Analog Channels
AN0, AN3 or AN6, to sample external signals, bit 11 of the CMxCON
register must be set to ‘1’.
The AC/DC electrical characteristics for the op amp module (and
the related ADC specifications) are not within the specifications
published in the current data sheet.
Dead-time compensation is not enabled for Center-Aligned PWM
mode.
The Stall mechanism may not function properly when erasing or
programming Flash memory.
The QEI Index Counter does not count correctly in Quadrature
Detector mode.
Modulo mode functionality is incorrect when the count polarity bit
is set.
In Master Time Base mode, writing to the period register and any
other timing parameter of the PWMx module, will cause the update
of the other timing parameter to take effect one PWM cycle after the
period update is effective.
Selecting the same ANx input (AN0 or AN3) for CH0 and CH1 to
achieve a 1.1 Msps sampling rate results in erroneous readings for
CH1.
Channel scanning is limited to AN0 through AN15.
Under certain circumstances, an output compare match may cause
the Output Compare x Interrupt Flag (OCxIF) bit to become set prior
to the Change-of-State (COS) of the OCx pin.
Write collisions on a DMA-enabled CAN module does not generate
DMAC error traps.
Dead time is not asserted when PDCx is updated to cause an
immediate transition on the PWMxH and PWMxL outputs.
PWMxH is asserted for 100% of the PWM period in Complementary
mode under certain circumstances.
With dead time greater than zero, 0% and 100% duty cycle cannot
be obtained on PWMxL and PWMxH outputs.
Op Amp
10.
PWM
Flash
QEI
QEI
PWM
11.
12.
13.
14.
15.
ADC
1.1 Msps Sampling
16.
ADC
Channel Scan
17.
18.
Output Compare
Interrupt
CAN
PWM
PWM
PWM
DMA
Immediate Update
Center-Aligned
Mode
Complementary
Mode
19.
20.
21.
22.
2011-2018 Microchip Technology Inc.
DS80000533N-page 5
