CD-700
Complete VCXO Based Phase Lock Loop
CD-700
Description
The VI CD-700 is a user-con gurable crystal based PLL integrated circuit. It includes a digital phase detector, op-amp, VCXO
and additional integrated functions for use in digital synchronization applications. Loop lter software is available as well SPICE
models for circuit simulation.
Features
•
•
•
•
•
•
•
•
•
5 x 7.5 x 2 mm, smallest VCXO PLL available
Output Frequencies to 77.76 MHz
5.0 or 3.3 Vdc operation
Tri-State Output
Holdover on Loss of Signal Alarm
VCXO with CMOS outputs
0/70 or –40/85 C temperature range
Hermetically sealed ceramic SMD package
Product is compliant to RoHS directive
•
•
•
•
•
•
•
Applications
Frequency Translation
Clock Smoothing, Clock Switching
NRZ Clock recovery
DSLAM, ADM, ATM, Aggregation, Optical Switching/Routing,
Base Station
Synchronous Ethernet
Low jitter PLL’s
Block Diagram
LOS
(8)
PHO OPN
(3)
(2)
OPOUT VC
(1)
(16)
LOSIN
(4)
DATAIN
(5)
CLKIN
(6)
Phase Detector and
LOS
VCXO
OUT1
(13)
Optional 2nd divider
OUT2
(11)
RCLK
(9)
RDATA
(10)
OPP
(15)
GND VDD
(7) (14)
HIZ
(12)
Page 1 of 12
Performance Speci cations
Table 1. Electrical Performance
Parameter
Output Frequency
(ordering option)
OUT 1, 5.0 V option
OUT 1, 3.3 V option
Supply Voltage
1
+5.0
+3.3
Supply Current
Output Logic Levels
Output Logic High
2
Output Logic Low
2
Output Transition Times
Rise Time
2
Fall Time
2
Input Logic Levels
Input Logic High
2
Input Logic Low
2
Loss of Signal Indication
Output Logic High
2
Output Logic Low
2
Nominal Frequency on Loss of Signal
Output 1
Output 2
Symmetry or Duty Cycle
3
Out 1
Out 2
RCLK
Absolute Pull Range
(ordering option)
over operating temperure, aging, and power
supply variations
Test Conditions for APR (+5.0 V option)
Test Conditions for APR (+3.3 V option)
Gain Transfer
Phase Detector Gain
+5.0 V option
+3.3 V option
Operating temperature
(ordering option)
Control Voltage Leakage Current
SYM1
SYM2
RCLK
APR
±50
±80
±100
0.5
0.3
Positive
0.53
0.35
T
OP
I
VCXO
0/70 or -40/85
±1.0
rad/V
rad/V
°C
A
4.5
3.0
V
DD
I
DD
V
OH
V
OL
t
R
t
F
V
IH
V
IL
V
OH
V
OL
2.0
0.5
2.5
0.5
±75
±75
40/60
45/55
40/60
2.5
0.5
3.0
3.0
Symbol
Min
1.000
1.000
4.5
2.97
Typical
Maximum
77.760
77.760
Units
MHz
MHz
V
V
mA
V
V
ns
ns
V
V
V
V
ppm
ppm
%
%
%
ppm
5.0
3.3
5.5
3.63
63
V
C
V
C
Kv
Kv
V
V
1. A 0.01uF and 0.1uF parallel capacitor should be located as close to pin 14 as possible (and grounded).
2. Figure 2 de nes these parameters. Figure 3 illustrates the equivalent ve gate TTL load and operating conditions under which these parameters
are tested and speci ed. Loads greater than 15 pF will adversely e ect rise/fall time as well as symmetry.
3. Symmetry is de ned as (ON TIME/PERIOD with Vs=1.4 V for both 5.0 V and 3.3 V operation.
Figure 2. Output Waveform
Page 2 of 12
Figure 3. OUT1, OUT2, RCLK, RDATA Test Conditions (25 ±5 C)
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied
at these or any other conditions in excess of conditions represented in the operational sections of this data sheet. Exposure to
absolute maximum ratings for extended periods may adversely a ect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Power Supply
Storage Temperature
Soldering Temperature/Duration
Clock and Data Input Range
Symbol
VDD
Tstorage
TPEAK / tP
CLKIN, DATAIN
Ratings
7
-55/125
260 / 40
Gnd-0.5 to V
DD
+0.5
Unit
Vdc
C
C/sec
V
Reliability
The CD-700 is capable of meeting the following quali cation tests:
Table 3. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014, 100% Tested
MIL-STD-883, Method 2016
Handling Precautions
Although ESD protection circuitry has been designed into the the CD-700, proper precautions should be taken when handling
and mounting. VI employs a Human Body Model (HBM) and a Charged Device Model (CDM) for ESD susceptibility testing and
design protection evaluation. ESD thresholds are dependent on the circuit parameters used to de ne the model.
Table 4. Predicted ESD R$atings
Model
Human Body Model
Charged Device Model
Minimum
1500 V
1000 V
Conditions
MIL-STD 883, Method 3015
JESD 22-C101
Page 3 of 12
CD-700 Theory of Operation
Phase Detector
The phase detector has two bu ered inputs (DATAIN and CLKIN) which are designed to switch at 1.4 volts. DATAIN is designed to
accept an NRZ data stream but may also be used for clock signals which have a 50% duty cycle. CLKIN is connected to OUT1 or
OUT2, or a divided version of one of these outputs. CLKIN and DATAIN and are protected by ESD diodes and should not exceed the
power supply voltage or ground by more than a few hundred millivolts.
The phase detector is basically a latched ip op/exclusive-or gate/di erential ampli er lter design to produce a DC signal
proportional to the phase between the CLKIN and DATAIN signals (see Figure 4 for a block diagram and Figure 5 for an open loop
transfer curve). This will simplify the PLL design as the designer does not have to lter narrow pulse signals to a DC level. Under
locked conditions the rising edge of CLKIN will be centered in the middle of the DATAIN signal (see Figure 6).
The phase detector gain is 0.53V/rad x data density for 5volt
operation and 0.35V/rad x data density for 3.3 volt opera-
tion. Data density is equal to 1.0 for clock signals and is
system dependent on coding and design for NRZ signals,
but 0.25 could be used as a starting point for data density.
The phase detector output is a DC signal for DATAIN fre-
quencies greater than 1 MHz but produces signi cant ripple
when inputs are less than 200 kHz. Additional ltering is
required for lower input frequencies applications such as
8kHz (see Figures 8 and 9 as examples).
Figure 4. Simpli ed Phase Detector Block Diagram
Under closed loop conditions the active lter has a block-
ing capacitor which provides a very high DC gain, so under
normal locked conditions and input frequencies >1 MHz, PHO will be about VDD/2 and will not vary signi cantly with changes in
input frequency (within lock range). The control voltage (pin 16) will vary according to the input frequency o set, but PHO will
remain relatively constant.
Recovered Clock and Data Alignment
Outputs
The CD-700 is designed to recover an embedded clock from
an NRZ data signal and retime it with a data pattern. In this
application, the VCXO frequency is exactly the same frequency
as the NRZ data rate and the outputs are taken o Pin 9 (RCLK),
and Pin 10 (RDATA). Under locked conditions, the falling edge of
RCLK is centered in the RDATA pattern. Also, there is a 1.5 clock
cycle delay between DATAIN and RDATA. Figure 6 shows the
relationship between the DATAIN, CLKIN, RDATA and RCLK.
Figure 5. Open Loop Phase Detecto Transfer Curve
Figure 6. Clock and Data Timing Relationships for the NRZ data
Other RZ encoding schemes such as Manchester or AMI can be accomodated by using a CD-700 at twice the baud rate.
Page 4 of 12
Loss of Signal, LOS and LOSIN
The LOS circuit provides an output alarm ag when the DATAIN input signal is lost. The LOS output is normally a logic low
and is set to a logic high after 256 consecutive clock periods on CLKIN with no detected DATAIN transitions. This signal can be
used to either ag external alarm circuits and/or drive the CD-700’s LOSIN input. When LOSIN is set to a logic high, the VCXO
control voltage (pin 16) is switched to an internal voltage which sets OUT1 and OUT2 to center frequency +/-75ppm. Also, LOS
automatically closes the op amp feedback which means the op-amp is a unity gain bu er and will produce a DC voltage equal to
the +op amp voltage (pin 15), usually VDD/2.
VCXO and Absolute Pull Range (APR) Speci cation
The CD-700’s VCXO is a varactor tuned crystal oscillator, which produces an output frequency proportional to the control voltage
(pin 16). The frequency deviation of the CD-700 VCXO is speci ed in terms of Absolute Pull Range (APR). APR provides the user
with a guaranteed speci cation for minimum available frequency deviation over all operating conditions. Operating conditions
include power supply variation, operating temperature range, and di erences in output loading and changes due to aging.
A CD-700 VCXO with an APR of +/-50 ppm will track a +/-50 ppm reference source over all operating conditions. The fourth
character of the product code in Table 7 speci es absolute Pull Range (APR). Please see Vectron’s web site (www.vectron.com) for
the APR Application Note. APR is tested at 0.5 and 4.5 volts for the 5.0 volt option and 0.3 and 3.0 volts for the 3.3 volt option.
VCXO Aging
Quartz oscillators typically exhibit a part per million shift in output frequency during aging. The major factors, which lead to this
shift, are changes in the mechanical stress on the crystal and mass-loading on the crystal.
As the oscillator ages, relaxation of the crystal mounting stress or transfer of environmental stress through the package to the
crystal mounting arrangement can lead to frequency variations. VI has minimized these two e ects through the use of a miniature
AT-cut strip resonator crystal which allows a superior mounting arrangement. This results in minimal relaxation and almost
negligible environmental stress transfer.
VI has eliminated the impact of mass loading by ensuring hermetic integrity and minimizing out-gassing by limiting the number
of internal components through the use of ASIC technology. Mass-loading on the crystal generally results in a frequency decrease
and is typically due to out-gassing of material within a hermetic package or from contamination by external material in a non-
hermetic package. Under normal operating conditions the CD-700 will typically exhibit 2 ppm aging in the rst year of operation.
The device will then typically exhibit 1 ppm aging the following year with a logarithmic decline each year thereafter.
Frequency Divider Feature
The lowest available VCXO OUT1 frequency is 1.000 MHz. To achieve lower frequencies, OUT1 is divided by a 2n counter (n = 1 to
8) and is the OUT2 frequency. The divider values (2, 4, 8, 16, 32, 64, 128 and 256) are set at the factory, so it is user selectable upon
ordering only. In addition, a disabled OUT2 option is also available. To achieve 1.024 MHz, a CD-700 with OUT1 frequency equal
to 16.384 MHz and a divider value equal to 16 would be used. Additional external divider circuits can be used to further lower or
change the frequency.
Loop Filter
A PLL is a feedback system which forces the output frequency to lock in both phase and frequency to the input frequency. While
there will be some phase error, theory states there is no frequency error. The loop lter design will dictate many key parameters
such as jitter reduction, stability, lock range and acquisition time. Be advised that many textbook equations describing loop
dynamics, such as capture range are based on ideal systems. Such equations may not be accurate for real systems due to
nonlinearities, DC o sets, noise and do not take into account the limited VCXO bandwidth. This section deals with some real world
design examples. Also, there is loop lter software on the Vectron web site, plus a full sta of experienced applications engineers
who are eager to assist in this process. Common CD-700 PLL applications are shown in Figures 8, 9 (frequency translation), Figure
10 (clock recovery) and Figure 11 (clock smoothing).
Page 5 of 12
FPGA/CPLD
