EB51F3A20N-40.000M
EB51F3 A 20 N -40.000M
Series
5.0Vdc 14-Pin DIP HCMOS/TTL TCXO
Operating Temperature Range
0°C to +50°C
Frequency Stability
±2.0ppm Maximum
Nominal Frequency
40.000MHz
Control Voltage
None (No Connect on Pin 1)
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Stability
Frequency Stability vs. Input Voltage
Aging at 25°C
Frequency Stability vs. Load
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Control Voltage
Internal Trim
Modulation Bandwidth
Input Impedance
Phase Noise
Storage Temperature Range
40.000MHz
±2.0ppm Maximum (Inclusive of Operating Temperature Range)
±0.3ppm Maximum (±5%)
±1ppm/Year Maximum
±0.2ppm Maximum (±2pF)
0°C to +50°C
5.0Vdc ±5%
30mA Maximum
2.4Vdc Minimum w/TTL Load, Vdd-0.5Vdc Minimum w/HCMOS Load
0.4Vdc Maximum w/TTL Load, 0.5Vdc Maximum w/HCMOS Load
10nSec Maximum (Measured at 0.4Vdc to 2.4Vdc w/TTL Load, 20% to 80% of waveform w/HCMOS Load)
50% ±10% (Measured at 1.4Vdc w/TTL Load, at 50% of waveform w/HCMOS Load)
10TTL Load or 15pF HCMOS Load Maximum
CMOS
None (No Connect on Pin 1)
±3ppm Minimum (Top of Can)
10kHz Minimum (Measured at -3dB with a Control Voltage of 2.5Vdc)
10kOhms Typical
-70dBc at 10Hz Offset, -100dBc at 100Hz Offset, -130dBc at 1kHz Offset, -140dBc at 10kHz Offset, -
145dBc at 100kHz Offset
-40°C to +85°C
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
Fine Leak Test
Gross Leak Test
Lead Integrity
Mechanical Shock
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 1014 Condition A (Internal Crystal Only)
MIL-STD-883, Method 1014 Condition C (Internal Crystal Only)
MIL-STD-883, Method 2004
MIL-STD-202, Method 213 Condition C
MIL-STD-202, Method 210
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010
MIL-STD-883, Method 2007 Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/16/2010 | Page 1 of 5
EB51F3A20N-40.000M
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
1
2
Internal Trim Access
Hole Ø3.5 ±0.5
3
4.8 ±0.3
5.0 ±1.0
4.0 ±0.3
11.7
±0.5
MARKING
ORIENTATION
2.5 ±0.3
7.62
±0.30
1.2 +0/-0.5
Ø0.50
±0.05
(x4)
3
4.0 ±0.3
4
4
CONNECTION
No Connect
Case Ground
Output
Supply Voltage
LINE MARKING
1
2
3
15.24 ±0.40
1
ECLIPTEK
40.000M
XXYZZ
XX=Ecliptek Manufacturing
Code
Y=Last Digit of the Year
ZZ=Week of the Year
18.3 ±0.5
2
OUTPUT WAVEFORM
CLOCK OUTPUT
V
OH
80% or 2.4V
DC
50% or 1.4V
DC
20% or 0.4V
DC
V
OL
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/16/2010 | Page 2 of 5
EB51F3A20N-40.000M
Test Circuit for TTL Output
Output Load
Drive Capability
10TTL
5TTL
2TTL
10LSTTL
1TTL
R
L
Value
(Ohms)
390
780
1100
2000
2200
C
L
Value
(pF)
15
15
6
15
3
Oscilloscope
Frequency
Counter
Table 1: R
L
Resistance Value and C
L
Capacitance
Value Vs. Output Load Drive Capability
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
R
L
(Note 4)
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
+
0.01µF
(Note 1)
0.1µF
(Note 1)
C
L
(Note 3)
Power
Supply
_
Ground
No Connect
or Tri-State
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and V
DD
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
Note 4: Resistance value R
L
is shown in Table 1. See applicable specification sheet for 'Load Drive Capability'.
Note 5: All diodes are MMBD7000, MMBD914, or equivalent.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/16/2010 | Page 3 of 5
EB51F3A20N-40.000M
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.01µF
(Note 1)
0.1µF
(Note 1)
Ground
C
L
(Note 3)
No Connect
or Tri-State
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and V
DD
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/16/2010 | Page 4 of 5
EB51F3A20N-40.000M
Recommended Solder Reflow Methods
T
P
Critical Zone
T
L
to T
P
Ramp-up
Ramp-down
Temperature (T)
T
L
T
S
Max
T
S
Min
t
S
Preheat
t 25°C to Peak
t
L
t
P
Time (t)
Low Temperature Solder Bath (Wave Solder)
T
S
MAX to T
L
(Ramp-up Rate)
Preheat
- Temperature Minimum (T
S
MIN)
- Temperature Typical (T
S
TYP)
- Temperature Maximum (T
S
MAX)
- Time (t
S
MIN)
Ramp-up Rate (T
L
to T
P
)
Time Maintained Above:
- Temperature (T
L
)
- Time (t
L
)
Peak Temperature (T
P
)
Target Peak Temperature (T
P
Target)
Time within 5°C of actual peak (t
p
)
Ramp-down Rate
Time 25°C to Peak Temperature (t)
Moisture Sensitivity Level
5°C/second Maximum
N/A
150°C
N/A
30 - 60 Seconds
5°C/second Maximum
150°C
200 Seconds Maximum
245°C Maximum
245°C Maximum 1 Time / 235°C Maximum 2 Times
5 seconds Maximum 1 Time / 15 seconds Maximum 2 Times
5°C/second Maximum
N/A
Level 1
Low Temperature Manual Soldering
185°C Maximum for 10 seconds Maximum, 2 times Maximum.
High Temperature Manual Soldering
260°C Maximum for 5 seconds Maximum, 2 times Maximum.
Low Temperature Solder Bath (Wave Solder) Note 1
Device is non-hermetic; Post reflow aqueous wash is not recommended
Low Temperature Solder Bath (Wave Solder) Note 2
Temperatures shown are applied to back of PCB board and device leads only.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/16/2010 | Page 5 of 5
