DATA SHEET
256MB Unbuffered DDR SDRAM DIMM
EBD25EC8AAFA
(32M words
×
72 bits, 1 Rank)
Description
The EBD25EC8AAFA is 32M words
×
72 bits, 1 rank
Double Data Rate (DDR) SDRAM unbuffered module,
mounting 9 pieces of 256M bits DDR SDRAM sealed in
TSOP package.
Read and write operations are
performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2 bits
prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology.
Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
•
184-pin socket type dual in line memory module
(DIMM)
PCB height: 31.75mm
Lead pitch: 1.27mm
•
2.5V power supply
•
Data rate: 266Mbps (max.)
•
2.5 V (SSTL_2 compatible) I/O
•
Double Data Rate architecture; two data transfers per
clock cycle
•
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
•
Data inputs and outputs are synchronized with DQS
•
4 internal banks for concurrent operation
(Component)
•
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
referenced to both edges of DQS
•
Auto precharge option for each burst access
•
Programmable burst length: 2, 4, 8
•
Programmable /CAS latency (CL): 2, 2.5
•
Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
•
2 variations of refresh
Auto refresh
Self refresh
EO
Document No. E0361E20 (Ver. 2.0)
Date Published May 2003 (K) Japan
URL: http://www.elpida.com
Elpida
Memory , Inc. 2003
L
od
Pr
uc
t
EBD25EC8AAFA
Ordering Information
Data rate
Component JEDEC speed bin
Mbps (max.) (CL-tRCD-tRP)
266
DDR 266B (2.5-3-3)
Contact
pad
Gold
Part number
EBD25EC8AAFA-7B
Package
184-pin DIMM
Mounted devices
M2S56D30ATP-75
Pin Configurations
Front side
1 pin
52 pin 53 pin
92 pin
EO
Pin No.
1
Pin name
VREF
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDD
CK1
/CK1
VSS
DQ10
DQ11
CKE0
VDD
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDD
Data Sheet E0361E20 (Ver. 2.0)
93 pin
Back side
144 pin 145 pin 184 pin
Pin No.
47
48
49
50
Pin name
DQS8
A0
CB2
VSS
CB3
BA1
DQ32
VDD
DQ33
Pin No.
93
94
95
96
97
98
99
100
101
Pin name
VSS
DQ4
DQ5
VDD
DM0/DQS9
DQ6
DQ7
VSS
NC
Pin No.
139
140
141
142
143
144
145
146
147
Pin name
VSS
DM8/DQS17
A10
CB6
VDD
CB7
VSS
DQ36
DQ37
VDD
DM4/DQS13
DQ38
DQ39
VSS
DQ44
/RAS
DQ45
VDD
/CS0
NC
DM5/DQS14
L
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
od
Pr
DQS4
102
NC
148
DQ34
103
NC
149
VSS
BA0
104
VDD
150
105
DQ12
151
DQ35
106
DQ13
152
DQ40
107
DM1/DQS10
153
VDD
/WE
108
VDD
154
109
DQ14
155
DQ41
110
DQ15
NC
156
/CAS
111
157
VSS
112
VDD
NC
158
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
/CK2
CK2
113
159
114
115
116
117
118
119
120
121
122
DQ20
A12
VSS
160
161
162
DQ21
A11
163
164
DM2/DQS11
VDD
DQ22
A8
165
166
167
168
uc
VSS
DQ46
DQ47
NC
VDD
DQ52
t
DQ53
NC
VDD
2
EBD25EC8AAFA
Pin No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Pin name
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
Pin No.
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Pin name
VDD
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Pin No.
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Pin name
DQ23
VSS
A6
DQ28
DQ29
VDD
DM3/DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDD
CK0
/CK0
Pin No.
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Pin name
DM6/DQS15
DQ54
DQ55
VDD
NC
DQ60
DQ61
VSS
DM7/DQS16
DQ62
DQ63
VDD
SA0
SA1
SA2
VDDSPD
EO
VSS
A1
CB0
45
46
CB1
VDD
Data Sheet E0361E20 (Ver. 2.0)
L
od
Pr
uc
t
3
EBD25EC8AAFA
Pin Description
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ63
CB0 to CB7
/RAS
/CAS
/WE
/CS0
Function
Address input
Row address
Column address
Data input/output
Check bit (Data input/output)
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
A0 to A12
A0 to A9
Bank select address
EO
CKE0
CK0 to CK2
/CK0 to /CK2
DQS0 to DQS8
SCL
SDA
SA0 to SA2
VDD
VDDSPD
VREF
VSS
VDDID
NC
Data Sheet E0361E20 (Ver. 2.0)
DM0 to DM8/DQS9 to DQS17
L
od
Pr
VDD identification flag
No connection
uc
t
4
EBD25EC8AAFA
Serial PD Matrix
Byte No.
0
1
2
3
4
5
6
7
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM ranks
Module data width
Module data width continuation
Bit7
1
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
Bit5 Bit4
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
Bit3
0
1
0
1
1
0
1
0
0
0
0
0
0
1
1
0
1
0
1
Bit2
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
Bit1 Bit0
0
0
1
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
1
0
1
0
0
0
1
1
0
0
0
0
1
0
0
0
Hex value
80H
08H
07H
0DH
0AH
01H
48H
00H
04H
75H
75H
02H
82H
08H
08H
01H
0EH
04H
0CH
01H
02H
20H
Comments
128 bytes
256 bytes
DDR SDRAM
13
10
1
72 bits
0
SSTL2
7.5ns
0.75ns
ECC
7.6µs
×
8
×
8
1 CLK
2,4,8
4
2, 2.5
0
1
Differential
Clock
VDD ± 0.2V
10ns
0.75ns
EO
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 to 26
27
28
29
30
31
32
33
Data Sheet E0361E20 (Ver. 2.0)
Voltage interface level of this assembly 0
0
0
0
1
0
0
0
0
0
0
0
0
DDR SDRAM cycle time, CL = 2.5
SDRAM access from clock (tAC)
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at CL = 2
Maximum data access time (tAC) from
0
clock at CL = 2
0
Minimum row precharge time (tRP)
Minimum row active to row active
delay (tRRD)
Minimum /RAS to /CAS delay (tRCD)
Minimum active to precharge time
(tRAS)
Module rank density
Address and command setup time
1
before clock (tIS)
Address and command hold time after
1
clock (tIH)
L
od
Pr
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
C0H
A0H
75H
00H
50H
20ns
15ns
3CH
50H
uc
20ns
2DH
40H
45ns
256M bytes
90H
90H
0.9ns
*1
0.9ns
*1
t
5
