PRELIMINARY DATA SHEET
2GB Unbuffered DDR3 SDRAM DIMM
EBJ21UE8BDF0 (256M words
×
64 bits, 2 Ranks)
Specifications
•
Density: 2GB
•
Organization
256M words
×
64 bits, 2 ranks
•
Mounting 16 pieces of 1G bits DDR3 SDRAM sealed
in FBGA
•
Package: 240-pin socket type dual in line memory
module (DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant) and Halogen-free
•
Power supply: VDD
=
1.5V
±
0.075V
•
Data rate: 1600Mbps/1333Mbps/1066Mbps (max.)
•
Eight internal banks for concurrent operation
(components)
•
Interface: SSTL_15
•
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
•
/CAS Latency (CL): 6, 7, 8, 9, 10, 11
•
/CAS write latency (CWL): 5, 6, 7, 8
•
Precharge: auto precharge option for each burst
access
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
Operating case temperature range
TC = 0°C to +95°C
Features
•
Double-data-rate architecture; two data transfers per
clock cycle
•
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
•
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
•
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Posted /CAS by programmable additive latency for
better command and data bus efficiency
•
On-Die-Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
•
Multi Purpose Register (MPR) for temperature read
out
•
ZQ calibration for DQ drive and ODT
•
Programmable Partial Array Self-Refresh (PASR)
•
/RESET pin for Power-up sequence and reset
function
•
SRT range:
Normal/extended
•
Programmable Output driver impedance control
Document No. E1515E10 (Ver. 1.0)
Date Published June 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2008-2009
EBJ21UE8BDF0
Ordering Information
Data rate
Mbps (max.)
1600
1333
Component
JEDEC speed bin
(CL-tRCD-tRP)
DDR3-1600K (11-11-11)
DDR3-1333H (9-9-9)
Contact
pad
Gold
Part number
EBJ21UE8BDF0-GN-F
EBJ21UE8BDF0-DJ-F
Package
240-pin DIMM
(lead-free and
halogen-free)
Mounted devices
EDJ1108BDSE-GL-F
EDJ1108BDSE-GN-F
EDJ1108BDSE-GL-F
EDJ1108BDSE-GN-F
EDJ1108BDSE-DJ-F
EDJ1108BDSE-GL-F
EDJ1108BDSE-GN-F
EDJ1108BDSE-DJ-F
EDJ1108BDSE-AE-F
EBJ21UE8BDF0-AE-F
1066
DDR3-1066F (7-7-7)
Preliminary Data Sheet E1515E10 (Ver. 1.0)
2
EBJ21UE8BDF0
Pin Configurations
Front side
1 pin
48 pin 49 pin
120 pin
121 pin
168 pin 169 pin
Back side
240 pin
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Pin name
VREFDQ
VSS
DQ0
DQ1
VSS
/DQS0
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
/DQS1
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
/DQS2
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
/DQS3
DQS3
VSS
DQ26
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Pin name
A2
VDD
CK1
/CK1
VDD
VDD
VREFCA
NC
VDD
A10(AP)
BA0
VDD
/WE
/CAS
VDD
/CS1
ODT1
VDD
NC
VSS
DQ32
DQ33
VSS
/DQS4
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
/DQS5
DQS5
VSS
DQ42
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
Pin name
VSS
DQ4
DQ5
VSS
DM0
NC
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
NC
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
NC
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DM3
NC
VSS
DQ30
DQ31
Pin No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
Pin name
A1
VDD
VDD
CK0
/CK0
VDD
NC
A0
VDD
BA1
VDD
/RAS
/CS0
VDD
ODT0
A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
NC
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5
NC
VSS
DQ46
DQ47
Preliminary Data Sheet E1515E10 (Ver. 1.0)
3
EBJ21UE8BDF0
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Pin name
DQ27
VSS
NC
NC
VSS
NC
NC
VSS
NC
NC
VSS
NC
NC
CKE0
VDD
BA2
NC
VDD
A11
A7
VDD
A5
A4
VDD
Pin No.
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Pin name
DQ43
VSS
DQ48
DQ49
VSS
/DQS6
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
/DQS7
DQS7
VSS
DQ58
DQ59
VSS
SA0
SCL
SA2
VTT
Pin No.
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Pin name
VSS
NC
NC
VSS
NC
NC
VSS
NC
NC
VSS
NC
/RESET
CKE1
VDD
NC
NC
VDD
A12
A9
VDD
A8
A6
VDD
A3
Pin No.
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Pin name
VSS
DQ52
DQ53
VSS
DM6
NC
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DM7
NC
VSS
DQ62
DQ63
VSS
VDDSPD
SA1
SDA
VSS
VTT
Preliminary Data Sheet E1515E10 (Ver. 1.0)
4
EBJ21UE8BDF0
Pin Description
Pin name
A0 to A13
A10 (AP)
A12 (/BC)
BA0, BA1, BA2
DQ0 to DQ63
/RAS
/CAS
/WE
/CS0, /CS1
CKE0, CKE1
CK0, CK1
/CK0, /CK1
DQS0 to DQS7, /DQS0 to /DQS7
DM0 to DM7
SCL
SDA
SA0, SA1, SA2
VDD
VDDSPD
VREFCA
VREFDQ
VSS
VTT
/RESET
ODT0, ODT1
NC
Function
Address input
Row address
Column address
Auto precharge
Burst chop
Bank select address
Data input/output
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Reference voltage for CA
Reference voltage for DQ
Ground
I/O termination supply for SDRAM
Set DRAM to known state
ODT control
No connection
A0 to A13
A0 to A9
Preliminary Data Sheet E1515E10 (Ver. 1.0)
5
