November 1996
Revision 1.0
DATA SHEET
EDC4BV724(2/4)-(60/70)(J/T)G-S
32MByte (4M x 72) CMOS
EDO DRAM Module - 3.3V (ECC), Buffered
General Description
The EDC4BV724(2/4)-(60/70)(J/T)G-S is a high performance, EDO (Extended Data Out) 32-megabyte dynamic RAM module
organized as 4M words by 72 bits, in a 168-pins, dual-in-line (DIMM) memory module with ECC.
The module utilizes eighteen, Fujitsu MB81V1(7/6)405A-(60/70)(PJ/FN) CMOS 4Mx4 EDO dynamic RAMs in a surface mount
package on an epoxy laminate substrate. Each device is accompanied by a decoupling capacitor for improved noise immunity.
Control lines provided are such that Dword control is possible. All signals are buffered (74ABT16244 or equivalent) except RAS,
data and IDs.
Features
• High Density: 32MByte
• Fast Access Time of 60/70 ns (max.)
• Low Power:
7.2/6.2 W (max.) - Active (60-70ns): 2KR
5.4/4.8 W (max.) -Active (60/70 ns): 4KR
360mW (max.) - Standby (LVTTL)
296mW (max.) - Standby (CMOS)
• LVTTL-compatible inputs and outputs
• Separate power and ground planes to improve noise immunity
• Single power supply of 3.3V±0.3V
• Height: 1.00 inch
• 2K/4K Refresh Cycles
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any pin relative to V
SS
Power Dissipation
Operating Temperature
Storage Temperate
Short Circuit Output Current
Symbol
V
T
P
T
T
opr
T
stg
I
OS
Ratings
-0.5 to +4.6
22
0 to +70
-55 to +125
-50 to +50
Unit
V
W
°
C
°
C
mA
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 to +70
°C)
Symbol
V
CC
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High voltage
Input Low voltage
Min
3.0
0
2.0
-0.3
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3
0.8
Unit
V
V
V
V
Fujitsu Microelectronics, Inc.
1
November 1996
Revision 1.0
EDC4BV724(2/4)-(60/70)(J/T)G-S
Functional Diagram
RAS0*
CAS0*
WE0*
OE0*
A0
DQ0~DQ35
RAS2*
4M x 36
BLOCK
CAS4*
WE2*
OE2*
B0
DQ36~DQ71
4M x 36
BLOCK
DQ0~DQ71
Notes: 1.
2.
3.
4.
5.
All signals including PDs (with the exception of RAS*, data and
IDs) are buffered.
“
*
” signifies active low signal.
Addresses A1~A10/A11 (A11 is NC for 2K Refresh modules) are
connected to all devices.
Each 4Mx36 Block comprises of nine 4Mx4 EDO devices.
All specifications of this device are subject to change without
notice.
V
CC
V
SS
Decoupling capacitors
to all devices
2
Fujitsu Microelectronics, Inc.
November 1996
Revision 1.0
EDC4BV724(2/4)-(60/70)(J/T)G-S
Pin Name
A0~A10, B0
A0~A9
A0~A11
DQ0~DQ71
WE0*, WE2*
RAS0*~RAS2*
OE0*, OE2*
CAS0*, CAS4*
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Rows and Column Addresses for 2KR
ColumnAddresses for 4KR
Row Addresses for 4KR
Data Inputs/Outputs
Write Enable
Row Address Strobes
Output Enable
Column Address Strobes
Pin No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
†
†
69
70
71
72
†
†
†
†
†
†
†
73
74
75
76
77
78
79
80
81
82
83
84
V
CC
V
SS
NC
PD1~PD8
PDE*
PD
PD6
PD7
Pin Designation
V
SS
DQ36
DQ37
DQ38
DQ39
V
CC
DQ40
DQ41
DQ42
DQ43
DQ44
V
SS
DQ45
DQ46
DQ47
DQ48
DQ49
V
CC
DQ50
DQ51
DQ52
DQ53
V
SS
NC
NC
V
CC
NC
NC
NC
NC
NC
V
SS
A1
A3
A5
A7
A9
A11 (Note)
NC
V
CC
NC
B0
†
†
†
†
†
†
†
Power Supply
Ground
No Connection
Presence Detect
Presence Detect Enable
60ns
70ns
NC
V
OL
NC
NC
Pin No.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin Designation
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
DQ16
DQ17
V
SS
NC
NC
V
CC
WE0*
CAS0*
NC
RAS0*
OE0*
V
SS
A0
A2
A4
A6
A8
A10
NC
V
CC
NC
NC
Pin Designation
V
SS
OE2*
RAS2*
CAS4*
NC
WE2*
V
CC
NC
NC
DQ18
DQ19
V
SS
DQ20
DQ21
DQ22‘
DQ23
V
CC
DQ24
NC
NC
NC
NC
DQ25
DQ26
DQ27
V
SS
DQ28
DQ29
DQ30
DQ31
V
CC
DQ32
DQ33
DQ34
DQ35
V
SS
PD1 (NC)
PD3 (V
OL
)
PD5 (NC)
PD7
ID0 (V
SS
)
V
CC
†
†
†
†
Pin No.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Pin Designation
V
SS
NC
NC
NC
NC
PDE*
V
CC
NC
NC
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
NC
NC
NC
NC
DQ61
DQ62
DQ63
V
SS
DQ64
DQ65
DQ66
DQ67
V
CC
DQ68
DQ69
DQ70
DQ71
V
SS
PD2 (NC)
PD4 (NC)
PD6
PD8 (V
OL
)
ID1 (V
SS
)
V
CC
†
Notes:
1.
2.
Signals marked with “†” are buffered.
A11 is NC for 2K refresh module.
Fujitsu Microelectronics, Inc.
3
November 1996
Revision 1.0
EDC4BV724(2/4)-(60/70)(J/T)G-S
DC CHARACTERISTICS
(V
CC
= 3.3V±0.3V, V
SS
= 0V, T
A
= 0 to +70
°C)
60
Parameter
Symbol
Test Condition
Min.
Operating Current
I
CC1
RAS*, CAS* cycling; t
RC
= min.
LVTTL Interface
RAS*, CAS*
≥
V
IH
D
out
= High-Z
CMOS Interface
RAS*, CAS*
≥
V
cc
- 0.2V
D
out
= High-Z
CAS*
≥
V
IH
; RAS*, Address
cycling @ t
RC
= min
RAS*, CAS* cycling @
t
RC
= min.
RAS*
≤
V
IL
CAS*, Address
cycling @ t
PC
= min
0V
≤
V
in
≤
V
CC
+0.3V
0V
≤
V
out
≤
V
CC
D
out
= Disable
High I
out
= -2mA
Low I
out
= 2 mA
2KR
4KR
2KR
4KR
2KR
4KR
2KR
4KR
-
-
-
Max.
1990
1504
46
Min.
-
-
-
Max.
1720
mA
1324
46
mA
1, 2
70
Unit
Note
Standby current
I
CC2
-
-
-
-
-
-
-
-90
-10
2.4
-
28
1990
1504
1990
1504
1864
1684
90
10
-
0.4
-
-
-
-
-
-
-
-90
-10
2.4
-
28
1720
mA
RAS* -only Refresh
Current
CAS*-before-RAS*
Refresh Current
Hyper Page Mode
Current
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Notes:
1.
2.
3.
I
CC3
mA
1324
1720
mA
1324
1684
mA
1504
90
10
-
0.4
2
I
CC4
I
CC5
I
LI
I
LO
V
OH
V
OL
1, 3
µ
A
µ
A
V
V
Values depend on output load condition when the device is selected. Maximum Values are specified at the output open condition.
Address can be changed once or less while RAS* = V
IL
.
Address can be changed once or less while CAS* = V
IH
.
CAPACITANCE
(TA =+25°C, V
CC
= 3.3V±0.3V)
Parameter
Input Capacitance (Address, CAS*, WE*, OE*)
Input Capacitance (RAS*)
Input/Output Capacitance (DQ0~DQ71)
Notes:
1.
2.
Symbol
C
I1
C
I2
C
I/O
Max.
13
70
12
Unit
pF
pF
pF
Note
1
1
1, 2
Capacitance is measured with Boonton Meter or effective capacitance method.
CAS* = V
IH
to disable D
out
.
4
Fujitsu Microelectronics, Inc.
November 1996
Revision 1.0
EDC4BV724(2/4)-(60/70)(J/T)G-S
AC CHARACTERISTICS
(TA = 0 to +70°C, V
CC
= 3.3V±0.3V, V
SS
= 0V)
Parameter
Random read/write cycle time
Access time from RAS*
Access time from CAS*
Access time from column address
Transition time (rise and fall)
RAS* precharge time
RAS* pulse width
RAS* hold time
CAS* hold time
CAS* pulse width
RAS* to CAS* delay time
RAS* to column address delay time
CAS* to RAS* precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS* lead time
Read command set-up time
Read command hold time to CAS*
Read command hold time to RAS*
Write command hold time
Write command pulse width
Write command to RAS* lead time
Write command to CAS* lead time
Data-in set-up time
Data-in hold time
Refresh period
Write command set-up time
CAS* set-up time (CBR refresh)
CAS* hold time (CBR refresh)
RAS* precharge to CAS* hold time
Access time from CAS* precharge
Hyper page mode cycle time
CAS* precharge time (Hyper page)
RAS* pulse width (Hyper page)
2KR
4KR
Symbol
t
RC
t
RAC
t
CAC
t
AA
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
REF
t
WCS
t
CSR
t
CHR
t
RPC
t
CPA
t
HPC
t
CP
t
RASP
60
Min
110
-
-
-
2
40
60
20
44
10
20
14
5
5
9
0
10
35
0
0
-1
10
10
20
10
-1
15
-
-
0
15
9
4
-
25
10
60
Max
-
60
20
35
50
-
10000
-
-
10000
45
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
32
64
-
-
-
-
40
-
-
100000
Min
130
-
-
-
2
50
70
25
49
15
20
14
5
5
9
0
15
40
0
0
-1
15
15
25
15
-1
20
-
-
0
15
14
4
-
30
10
70
70
Max
-
70
25
40
50
-
10000
-
-
10000
50
30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
32
64
-
-
-
-
45
-
-
100000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
12
3, 11
7
1
1
9
9
8
4
10
3,4
3,4,5
3, 10
2
Notes
Fujitsu Microelectronics, Inc.
5
