PRELIMINARY DATA SHEET
512M bits DDR SDRAM
WTR (Wide Temperature Range)
EDD5108AGTA-LI (64M words
×
8 bits)
EDD5116AGTA-LI (32M words
×
16 bits)
Specifications
•
Density: 512M bits
•
Organization
⎯
16M words
×
8 bits
×
4 banks (EDD5108AGTA)
⎯
8M words
×
16 bits
×
4 banks (EDD5116AGTA)
•
Package: 66-pin plastic TSOP (II)
⎯
Lead-free (RoHS compliant)
•
Power supply: VDD, VDDQ
=
2.5V
±
0.2V
•
Data rate: 400Mbps/333Mbps/266Mbps (max.)
•
Four internal banks for concurrent operation
•
Interface: SSTL_2
•
Burst lengths (BL): 2, 4, 8
•
Burst type (BT):
⎯
Sequential (2, 4, 8)
⎯
Interleave (2, 4, 8)
•
/CAS Latency (CL): 2, 2.5, 3
•
Precharge: auto precharge option for each burst
access
•
Driver strength: normal/weak
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles: 8192 cycles/64ms
⎯
Average refresh period: 7.8μs
•
Operating ambient temperature range
⎯
TA = –40°C to +85°C
Features
•
Double-data-rate architecture; two data transfers per
clock cycle
•
The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
•
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
•
Data inputs, outputs, and DM are synchronized with
DQS
•
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
·Wide temperature range
⎯
TA = –40°C to +85°C
Document No. E1304E10 (Ver. 1.0)
Date Published April 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida
Memory, Inc. 2008
EDD5108AGTA-LI, EDD5116AGTA-LI
Ordering Information
Part number
EDD5108AGTA-5BLI-E
EDD5108AGTA-5CLI-E
EDD5108AGTA-6BLI-E
EDD5108AGTA-7ALI-E
EDD5108AGTA-7BLI-E
EDD5116AGTA-5BLI-E
EDD5116AGTA-5CLI-E
EDD5116AGTA-6BLI-E
EDD5116AGTA-7ALI-E
EDD5116AGTA-7BLI-E
Mask
version
G
Organization
(words
×
bits)
64M
×
8
Internal
banks
4
Data rate
Mbps (max.)
400
333
266
32M
×
16
400
333
266
JEDEC speed bin
(CL-tRCD-tRP)
DDR400B (3-3-3)
DDR400C (3-4-4)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR400B (3-3-3)
DDR400C (3-4-4)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
Package
66-pin Plastic
TSOP (II)
Part Number
E D D 51 08 A G TA - 5B LI - E
Elpida Memory
Environment Code
E: Lead Free
(RoHS compliant)
Spec Detail
LI: WTR (−40°C to +85°C)
& Low Power
Speed
5B: DDR400B (3-3-3)
5C: DDR400C (3-4-4)
6B: DDR333B (2.5-3-3)
7A: DDR266A (2-3-3)
7B: DDR266B (2.5-3-3)
Package
TA: TSOP (II)
Die Rev.
Type
D: Monolithic Device
Product Family
D: DDR SDRAM
Density / Bank
51: 512M / 4-bank
Organization
08: x8
16: x16
Power Supply, Interface
A: 2.5V, SSTL_2
Speed Grade Compatibility
Operating Frequencies
Speed bin
DDR400B
DDR400C
DDR333B
DDR266A
DDR266B
CL2
133MHz
133MHz
133MHz
133MHz
100MHz
CL2.5
166MHz
166MHz
166MHz
133MHz
133MHz
CL3
200MHz
200MHz
166MHz
133MHz
133MHz
Preliminary Data Sheet E1304E10 (Ver. 1.0)
2
EDD5108AGTA-LI, EDD5116AGTA-LI
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD
VDD
DQ0
DQ0
VDDQ VDDQ
NC
DQ1
DQ1
DQ2
VSSQ VSSQ
NC
DQ3
DQ2
DQ4
VDDQ VDDQ
NC
DQ5
DQ3
DQ6
VSSQ VSSQ
NC
DQ7
NC
NC
VDDQ VDDQ
NC LDQS
NC
NC
VDD
VDD
NC
NC
NC
LDM
/WE
/WE
/CAS
/CAS
/RAS
/RAS
/CS
/CS
NC
NC
BA0
BA0
BA1
BA1
A10(AP) A10(AP)
A0
A0
A1
A1
A2
A2
A3
A3
VDD
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS VSS
DQ15 DQ7
VSSQ VSSQ
DQ14 NC
DQ13 DQ6
VDDQ VDDQ
DQ12 NC
DQ11 DQ5
VSSQ VSSQ
DQ10 NC
DQ9 DQ4
VDDQ VDDQ
DQ8 NC
NC
NC
VSSQ VSSQ
UDQS DQS
NC
NC
VREF VREF
VSS VSS
UDM DM
/CK /CK
CK
CK
CKE CKE
NC
NC
A12 A12
A11 A11
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
VSS VSS
X 16
X8
(Top view)
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ15
DQS, LDQS, UDQS
/CS
/RAS
/CAS
/WE
DM, UDM, LDM
Function
Address inputs
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe
Column address strobe
Write enable
Input mask
Pin name
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
Function
Clock input
Differential Clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Preliminary Data Sheet E1304E10 (Ver. 1.0)
3
EDD5108AGTA-LI, EDD5116AGTA-LI
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Speed Grade Compatibility............................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Specifications.................................................................................................................................5
Block Diagram .............................................................................................................................................13
Pin Function.................................................................................................................................................14
Command Operation ...................................................................................................................................16
Simplified State Diagram .............................................................................................................................23
Operation of the DDR SDRAM ....................................................................................................................24
Timing Waveforms.......................................................................................................................................43
Package Drawing ........................................................................................................................................49
Recommended Soldering Conditions..........................................................................................................50
Preliminary Data Sheet E1304E10 (Ver. 1.0)
4
EDD5108AGTA-LI, EDD5116AGTA-LI
Electrical Specifications
•
All voltages are referenced to VSS (GND).
•
After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
Symbol
VT
VDD
IOS
PD
TA
Tstg
Rating
–1.0 to +3.6
–1.0 to +3.6
50
1.0
–40 to +85
–55 to +125
Unit
V
V
mA
W
°C
°C
Note
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions (TA = –40°C to +85°C)
Parameter
Supply voltage
Symbol
VDD, VDDQ
VSS, VSSQ
Input reference voltage
Termination voltage
Input high voltage
Input low voltage
Input voltage level,
CK and /CK inputs
Input differential cross point
voltage, CK and /CK inputs
Input differential voltage,
CK and /CK inputs
VREF
VTT
VIH (DC)
VIL (DC)
VIN (DC)
VIX (DC)
VID (DC)
min.
2.3
0
0.49
×
VDDQ
VREF – 0.04
VREF + 0.15
–0.3
–0.3
0.5
×
VDDQ
−
0.2V
0.36
typ.
2.5
0
0.50
×
VDDQ
VREF
—
—
—
0.5
×
VDDQ
—
max.
2.7
0
0.51
×
VDDQ
VREF + 0.04
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
0.5
×
VDDQ + 0.2V
VDDQ + 0.6
Unit
V
V
V
V
V
V
V
V
V
5, 6
2
3
4
Notes
1
Notes: 1.
2.
3.
4.
5.
6.
VDDQ must be lower than or equal to VDD.
VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
VIN (DC) specifies the allowable DC execution of each differential input.
VID (DC) specifies the input differential voltage required for switching.
VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.
Preliminary Data Sheet E1304E10 (Ver. 1.0)
5
测试/测量
