White Electronic Designs
PCMCIA Flash Memory Card
8MB Through 64 MB (AMD based)
FEATURES
Very High Density Linear Flash Card
Supports 5V only systems
Based on AMD Flash Components
• Low standby power without entering reset mode
• Allows standard access from standby mode
Fast Read Performance
• 150ns Maximum Access Time
x8/ x16 Data Interface
High Performance Random Writes
• 7µs Typical Word Write Time
Automated Write and Erase Algorithms
• AMD Command Set
1,000,000 Erase Cycles per Block
64K word (128kB) symmetrical Block Architecture
PC Card Standard Type I Form Factor
PCMCIA Flash Memory Card
FLE Series
ARCHITECTURE OVERVIEW
WEDC’s FLE series is designed to support up to twenty (see
Block diagram) 32Mb components, providing a wide range
of density options. Cards are based on the Am29F032
(32Mb) device for 5V only applications. The device code
for the Am29F032 is 41h and the manufacturer’s ID is 01h.
Systems should be able to recognize these codes. Cards
utilizing 32Mb components provide densities ranging from
8MB to 64MB in 8MB increments.
In support of the PC Card (PCMCIA) standard for word
wide access, devices are paired. Therefore, the Flash
array is structured in 64K word blocks. Write, read and
block erase operations can be performed as either a
word or byte wide operation . By multiplexing A0, CE1#
and CE2#, 8-bit hosts can access all data on data lines
DQ0 - DQ7. The FLE series cards conform with the PC
Card Standard (formerly PCMCIA) and supported JEIDA,
providing electrical and physical compatibility. The PC
Card form factor offers an industry standard pinout and
mechanical outline, allowing density upgrades without
system design changes.
WEDC’s standard cards are shipped with WEDC’s
silkscreen design. Cards are also available with blank
housings (no silkscreen). The blank housings are available
in both a recessed (for label) and flat housing. Please
contact your WEDC sales representative for further
information on Custom artwork.
GENERAL DESCRIPTION
WEDC’s PCMCIA Flash memory cards offer the highest
density, linear Flash solid state storage solutions for code
and data storage, high performance disk emulation and
execute in place (XIP) applications in mobile PC and
dedicated (embedded) equipment.
Packaged in a PCMCIA type I housing, each card contains
a connector, an array of Flash memories packaged in
TSOP packages and card control logic. The card control
logic provides the system interface and controls the
internal Flash memories. Combined with file management
software, such as Flash Translation Layer (FTL), WEDC
Flash cards provide removable high-performance disk
emulation.
The WEDC FLE series is based on AMD Flash memories.
The FLE series offers byte wide and word wide operation,
low power modes and Card Information Structure (CIS)
for easy identification of card characteristics.
Note: Standard options include attribute memory. Cards without attribute memory are
available. Cards are also available with or without a hardware write protect switch.
August 2000
Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PCMCIA Flash Memory Card
FLE Series
FLE BLOCK DIAGRAM
Device type
Am29F032
Manuf ID
01
H
Device ID
41
H
Device Pair (N/2 - 1)
Device (N-1)
Device (N-2)
CSn
Array
Address
Bus
ADDRESS
BUFFER
ADDRESS BUS
A1-A25
Control
Address
Bus
M Res
WL#
RL#
WH#
RH#
CSn
Device 3
Device 2
CS1
CS0
Q2
Q0
Ctrl
At/Reg enable
Control Logic
PCMCIA Interface
Qn
WE#
OE#
CE2#
CE1#
REG#
A0
WP
Device Pair 1
Device Pair 0
Device 1
Device 0
CS0
Vcc
WH# RH#
DATA
BUS
Q8-Q15
DATA
BUS
Q0-Q7
WL# RL#
0000h
attrib. mem
CIS
EEPROM 2kB
Vcc
control
Q0-Q7
Vcc
I/O buffer
DATA
BUS
D8-D15
DATA
BUS
D0-D7
August 2000
Rev. 4
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PINOUT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal name
GND
DQ3
DQ4
DQ5
DQ6
DQ7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
RDY/BSY#
Vcc
Vpp1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
WP
GND
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
O
Function
Ground
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Card enable 1
Address bit 10
Output enable
Address bit 11
Address bit 9
Address bit 8
Address bit 13
Address bit 14
Write Enable
Ready/Busy
Supply Voltage
Prog. Voltage
Address bit 16
Address bit 15
Address bit 12
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Data bit 0
Data bit 1
Data bit 2
Write Potect
Ground
Active
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
PCMCIA Flash Memory Card
FLE Series
LOW
LOW
LOW
LOW
N.C.
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
HIGH
Signal name
GND
CD1#
DQ11
DQ12
DQ13
DQ14
DQ15
CE2#
VS1
RFU
RFU
A17
A18
A19
A20
A21
Vcc
Vpp2
A22
A23
A24
A25
VS2
RST
Wait#
RFU
REG#
BVD2
BVD1
DQ8
DQ9
DQ10
CD2#
GND
I/O
O
I/O
I/O
I/O
I/O
I
I
O
I
I
I
I
I
O
I
O
I
O
O
I/O
I/O
O
O
Function
Ground
Card Detect 1
Data bit 11
Data bit 12
Data bit 13
Data bit 14
Data bit 15
Card Enable 2
Voltage Sense 1
Reserved
Reserved
Address bit 17
Address bit 18
Address bit 19
Address bit 20
Address bit 21
Supply Voltage
Prog. Voltage
Address bit 22
Address bit 23
Address bit 24
Address bit 25
Voltage Sense 2
Card Reset
Extended Bus Cycle
Reserved
Attrib Mem Select
Bat. Volt. Detect 2
Bat. Volt. Detect 1
Data bit 8
Data bit 9
Data bit 10
Card Detect 2
Ground
Active
LOW
LOW
N.C.
N.C.
8MB (3)
16MB (3)
32MB (3)
64MB (3)
N.C.
HIGH
LOW (2)
(2)
(2)
LOW
Notes:
1. RDY/BSY is an open drain output, external pull-up resistor is required.
2. Wait#, BVD1 and BVD2 are driven high for compatibility.
3. Shows density for which specified address bit is MSB. Higher order address bits are
no connects (i.e., 16MB A23 is MSB A24, A25 are NC).
August 2000
Rev. 4
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PCMCIA Flash Memory Card
FLE Series
PACKAGE DIMENSIONS
0.063
3.370
0.039
2.126
0.039
0.400
0.130
MAX.
August 2000
Rev. 4
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PCMCIA Flash Memory Card
FLE Series
CARD SIGNAL DESCRIPTION
Symbol
A0 - A25
DQ0 - DQ15
CE1#, CE2#
OE#
WE#
RDY/BSY#
Type
INPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
OUTPUT
Name and Function
ADDRESS INPUTS:
A0 through A25 enable direct addressing of up to 64MB of memory on the card. Signal A0 is not
used in word access mode. A25 is the most significant bit
DATA INPUT/OUTPUT:
DQ0 THROUGH DQ15 constitute the bi-directional databus. DQ15 is the MSB.
CARD ENABLE 1 AND 2:
CE1# enables even byte accesses, CE2# enables odd byte accesses. Multiplexing A0,
CE1# and CE2# allows 8-bit hosts to access all data on DQ0 - DQ7.
OUTPUT ENABLE:
Active low signal gating read data from the memory card.
WRITE ENABLE:
Active low signal gating write data to the memory card.
READY/BUSY OUTPUT:
Indicates status of internally timed erase or program algorithms. A high output indicates that
the card is ready to accept accesses. A low output indicates that one or more devices in the memory card are busy
with internally timed erase or write activities.
CARD DETECT 1 and 2:
Provide card insertion detection. These signals are connected to ground internally on the
memory card. The host socket interface circuitry shall supply 10K-ohm or larger pull-up resistors on these signal pins.
WRITE PROTECT:
Write protect reflects the status of the Write Protect switch on the memory card. WP set to high
= write protected, providing internal hardware write lockout to the Flash array. If card does not include optional write
protect switch, this signal will be pulled low internally indicating write protect = “off”.
PROGRAM/ERASE POWER SUPPLY:
Not connected for 5V only card.
CARD POWER SUPPLY:
5.0V for all internal circuitry.
GROUND:
for all internal circuitry.
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
ATTRIBUTE MEMORY SELECT:
provides access to Flash memory card registers and Card Information Structure in
the Attribute Memory Plane.
RESET:
Active high signal for placing card in Power-on default state. Reset can be used as a Power-Down signal for
the memory array.
WAIT:
This signal is pulled high internally for compatibility. No wait states are generated.
BATTERY VOLTAGE DETECT:
These signals are pulled high to maintain SRAM card compatibility.
VOLTAGE SENSE:
Notifies the host socket of the card’s VCC requirements. VS1 and VS2 are open to indicate a 5V
card has been inserted.
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD:
pin may be driven or left floating
CD1#, CD2#
WP
OUTPUT
OUTPUT
VPP1, VPP2
VCC
GND
REG#
RST
WAIT#
BVD1, BVD2
VS1, VS2
RFU
N.C.
N.C.
August 2000
Rev. 4
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
