EDI88257CA
HI-RELIABILITY PRODUCT
256Kx8 Monolithic SRAM
FEATURES
s
Access Times of 20, 25, 35, 45, 55ns
s
Data Retention Function (LPA Versions)
s
TTL Compatible Inputs and Outputs
s
Fully Static, No Clocks
s
Organized as 256Kx8
s
Commercial, Industrial and Military Temperature Ranges
s
JEDEC Approved Evolutionary Pinout
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)
s
Single +5V (±10%) Supply Operation
The EDI88257CA is a 2 Megabit 256Kx8 bit Monolithic CMOS
Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolutionary standard
for the two megabit device. The device is upgradeable to the
512Kx8 SRAM, the EDI88512CA. Pin 1 becomes the higher order
address.
A Low Power version, EDI88257LPA, offers a data retention
function for battery back-up opperation. Military product is avail-
able compliant to Appendix A of MIL-PRF-38535.
FIG. 1
PIN CONFIGURATION
PIN DESCRIPTION
32 DIP
I/O
0-7
A
0-17
32 V
CC
31 A15
30 A17
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CS
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
A
Ø-17
TOP VIEW
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
AØ
I/OØ
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power (+5V
±10%)
Ground
Not Connected
WE
CS
OE
V
CC
V
SS
BLOCK DIAGRAM
Memory Array
NC
Address
Buffer
Address
Decoder
I/O
Circuits
I/O
Ø-7
WE
CS
OE
May 2000 Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88257CA
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Operating Temperature T
A
(Ambient)
Industrial
Military
Storage Temperature, Ceramic
Power Dissipation
Output Current
Junction Temperature, T
J
-40 to +85
-55 to +125
-65 to +150
1.5
20
175
°C
°C
°C
W
mA
°C
-0.5 to 7.0
Unit
V
OE
X
H
L
X
CS
H
L
L
L
WE
X
H
H
L
TRUTH TABLE
Mode
Standby
Output Deselect
Read
Write
Output
High Z
High Z
Data Out
Data In
Power
Icc
2
, Icc
3
Icc
1
Icc
1
Icc
1
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.3
Typ
5.0
0
—
—
Max
5.5
0
Vcc +0.5
+0.8
Unit
V
V
V
V
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indi-
cated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25°C)
Parameter
Address Lines
Input/Output Lines
Symbol
C
I
C
O
Condition
V
IN
= Vcc or Vss, f = 1.0MHz
V
OUT
= Vcc or Vss, f = 1.0MHz
Max
12
14
Unit
pF
pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
(V
CC
= 5V, T
A
= +25°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
CC3
V
OL
V
OH
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
WE, CS = V
IL
, I
I/O
= 0mA, Min Cycle
CS
≥
V
IH
, V
IN
≤
V
IL
, V
IN
≥
V
IH
CS
≥
V
CC
-0.2V
V
IN
≥
Vcc -0.2V or V
IN
≤
0.2V
I
OL
= 8.0mA
I
OH
= -4.0mA
CA
LPA
(20-25ns)
(35-55ns)
Conditions
Min
-10
-10
—
—
—
—
—
—
2.4
—
—
—
—
Typ
—
—
Max
+10
+10
225
200
60
25
20
0.4
—
µA
µA
mA
mA
mA
mA
mA
V
V
Units
NOTE: DC test conditions: V
IL
= 0.3V, V
IH
= Vcc -0.3V
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
2
EDI88257CA
AC CHARACTERISTICS – READ CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C))
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z (1)
Symbol
JEDEC
Alt.
t
AVAV
t
AVQV
t
ELQV
t
ELQX
t
EHQZ
t
AVQX
t
GLQV
t
GLQX
t
GHQZ
t
RC
t
AA
t
ACS
t
CLZ
t
CHZ
t
OH
t
OE
t
OLZ
t
OHZ
0
0
8
3
0
0
10
0
0
10
8
20ns
Min
Max
20
20
20
3
0
0
12
0
0
15
10
25ns
Min
25
25
25
3
0
0
15
0
0
20
15
Max
35ns
Min
Max
35
35
35
3
0
0
25
0
0
20
20
45ns
Min
Max
45
45
45
3
0
0
25
20
55ns
Min
Max
55
55
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
Symbol
JEDEC
Alt.
t
AVAV
t
ELWH
t
ELEH
t
AVWL
t
AVEL
t
AVWH
t
AVEH
t
WLWH
t
WLEH
t
WHAX
t
EHAX
t
WHDX
t
EHDX
t
WLQZ
t
DVWH
t
DVEH
t
WHQX
t
WC
t
CW
t
CW
t
AS
t
AS
t
AW
t
AW
t
WP
t
WP
t
WR
t
WR
t
DH
t
DH
t
WHZ
t
DW
t
DW
t
WLZ
20ns
Min
Max
20
15
15
0
0
15
15
15
15
0
0
0
0
0
10
10
0
8
Min
25
17
17
0
0
17
17
17
17
0
0
0
0
0
12
12
0
10
25ns
Max
35ns
Min
Max
35
25
25
0
0
25
25
25
25
0
0
0
0
0
20
20
0
25
45ns
Min
Max
45
30
30
0
0
30
30
30
30
0
0
0
0
0
25
25
0
30
55ns
Min
Max
45
30
30
0
0
30
30
30
30
0
0
0
0
0
25
25
0
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
480Ω
480Ω
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
V
SS
to 3.0V
5ns
1.5V
Figure 1
NOTE:
For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2)
Q
255Ω
30pF
Q
255Ω
5pF
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88257CA
FIG. 2
TIMING WAVEFORM - READ CYCLE
ADDRESS
t
AVAV
t
AVQV
t
AVAV
ADDRESS
ADDRESS 1
ADDRESS 2
CS
t
ELQV
t
ELQX
OE
t
EHQZ
t
AVQV
DATA I/O
t
AVQX
DATA 1
DATA 2
t
GLQV
t
GLQX
DATA OUT
t
GHQZ
READ CYCLE 1 (WE HIGH; OE, CS LOW)
READ CYCLE 2 (WE HIGH)
FIG. 3
WRITE CYCLE - WE CONTROLLED
t
AVAV
ADDRESS
t
AVWH
t
ELWH
CS
t
WHAX
t
AVWL
WE
t
WLWH
t
DVWH
t
WHDX
DATA IN
DATA VALID
t
WLQZ
DATA OUT
HIGH Z
t
WHQX
WRITE CYCLE 1, WE CONTROLLED
FIG. 4
WRITE CYCLE - CS CONTROLLED
ADDRESS
t
AVAV
WS32K32-XHX
t
AVEH
t
ELEH
t
EHAX
t
AVEL
t
WLEH
t
DVEH
t
EHDX
CS
WE
DATA IN
DATA OUT
HIGH Z
DATA VALID
WRITE CYCLE 2, CS CONTROLLED
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
4
EDI88257CA
DATA RETENTION CHARACTERISTICS (EDI88257LPA ONLY)
(T
A
= -55°C to +125°C)
Characteristic
Low Power Version only
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time
Operation Recovery Time
Sym
V
DD
I
CCDR
T
CDR
T
R
Conditions
V
DD
= 2.0V
CS
≥
V
DD
-0.2V
V
IN
≥
V
DD
-0.2V
or V
IN
≤
0.2V
Min
2
–
0
T
AVAV
Typ
–
–
–
–
Max
–
2
–
–
Units
V
mA
ns
ns
FIG. 5
DATA RETENTION - CS CONTROLLED
Data Retention Mode
Vcc
4.5V
V
DD
WS32K32-XHX
4.5V
t
CDR
CS
CS = V
DD
-0.2V
t
R
DATA RETENTION, CS CONTROLLED
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
