EDI88512CA
512Kx8 Monolithic SRAM, SMD 5962-95600
FEATURES
Access Times of 15, 17, 20, 25, 35, 45, 55ns
Data Retention Function (LPA version)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Organized as 512Kx8
Commercial, Industrial and Military Temperature Ranges
32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic Sidebrazed 400 mil DIP (Package 326)
• Ceramic 32 pin Flatpack (Package 344)
• Ceramic Thin Flatpack (Package 321)
• Ceramic SOJ (Package 140)
36 lead JEDEC Approved Revolutionary Pinout
• Ceramic Flatpack (Package 316)
• Ceramic SOJ (Package 327)
• Ceramic LCC (Package 502)
Single +5V (±10%) Supply Operation
*This product is subject to change without notice.
The EDI88512CA is a 4 megabit Monolithic CMOS Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolutionary standard
for the four megabit device. All 32 pin packages are pin for pin
upgrades for the single chip enable 128K x 8, the EDI88128CS.
Pins 1 and 30 become the higher order addresses.
The 36 pin revolutionary pinout also adheres to the JEDEC
standard for the four megabit device. The center pin power and
ground pins help to reduce noise in high performance systems.
The 36 pin pinout also allows the user an upgrade path to the
future 2Mx8.
A Low Power version with Data Retention (EDI88512LPA) is
also available for battery backed applications. Military product is
available compliant to Appendix A of MIL-PRF-38535.
FIGURE 1 – PIN CONFIGURATION
I/O
0-7
A0
-18
WE#
CS#
OE#
PIN DESCRIPTION
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power (+5V ±10%)
Ground
Not Connected
36 PIN
TOP VIEW
A0
A1
A2
A3
A4
CS#
I/O0
I/O1
Vcc
Vss
I/O2
I/O3
WE#
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
36 pin
9
10
Revolutionary
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE#
I/O7
I/O6
Vss
Vcc
I/O5
I/O4
A14
A13
A12
A11
A10
NC
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 PIN
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
V
CC
V
SS
NC
BLOCK DIAGRAM
Memory Array
32 pin
Evolutionary
A
0-18
Address
Buffer
Address
Decoder
I/O
Circuits
I/O
0-7
WE#
CS#
OE#
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 15
© 2014 Microsemi Corporation. All rights reserved.
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Operating Temperature T
A
(Ambient)
Commercial
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, T
J
0
T
A
+70
-40
T
A
+85
-55
T
A
+125
-65
T
A
+150
1.5
20
175
°C
°C
°C
°C
W
mA
°C
Value
-0.5 to 7.0
Unit
V
OE#
X
H
L
X
CS#
H
L
L
L
WE#
X
H
H
L
TRUTH TABLE
Mode
Standby
Output Deselect
Read
Write
Output
High Z
High Z
Data Out
Data In
Power
Icc
2
, Icc
3
Icc1
Icc1
Icc1
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.3
Typ
5.0
0
—
—
Max
5.5
0
V
CC
+ 0.3
+0.8
Unit
V
V
V
V
NOTE:
Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this speci
fi
cation is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25°C)
Parameter
Address Lines
Data Lines
Symbol
C
I
C
O
Condition
V
IN
= Vcc or Vss, f = 1.0MHz
V
OUT
= Vcc or Vss, f = 1.0MHz
Max
12
14
Unit
pF
pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
(V
CC
= 5V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Output Low Voltage
Output High Voltage
NOTE: DC test conditions: V
IL
= 0.3V, V
IH
= Vcc -0.3V
Symbol
I
LI
I
LO
I
CC
1
I
CC2
I
CC3
V
OL
V
OH
V
IN
= 0V to V
CC
V
I
/
O
= 0V to V
CC
Conditions
Min
-10
-10
(17ns)
(20 -55ns)
CA
LPA
—
—
—
—
—
—
2.4
Max
10
10
250
225
60
25
20
0.4
—
Units
μA
μA
mA
mA
mA
mA
mA
V
V
WE#, CS# = V
IL
, I
I
/
O
= 0mA, Min Cycle
CS#
V
IH
, V
IN
V
IL
, V
IN
V
IH
CS#
V
CC
-0.2V
V
IN
Vcc -0.2V or V
IN
0.2V
I
OL
= 6.0mA
I
OH
= -4.0mA
AC TEST CONDITIONS
Figure 1
Figure 2
Vcc
Vcc
Input Pulse Levels
480Ω
480Ω
V
SS
to 3.0V
5ns
1.5V
Figure 1
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Q
255Ω
30pF
Q
255Ω
5pF
NOTE: For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2)
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 15
© 2014 Microsemi Corporation. All rights reserved.
2
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA
AC CHARACTERISTICS – READ CYCLE
(V
CC
= 5.0V, Vss = 0V, -55°C
≤
T
A
≤
+125°C)
Symbol
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
JEDEC
t
AVAV
t
AVQV
t
ELQV
t
ELQX
t
EHQZ
t
AVQX
t
GLQV
t
GLQX
t
GHQZ
Alt.
t
RC
t
AA
t
ACS
t
CLZ
t
CHZ
t
OH
t
OE
t
OLZ
t
OHZ
0
0
7
2
0
0
8
0
0
7
7
15
15
15
3
0
0
8
0
0
8
7
15ns
Min
Max
17
17
17
3
0
0
10
0
0
10
8
17ns
Min
Max
20
20
20
3
0
0
12
0
0
15
10
20ns
Min
Max
25
25
25
3
0
0
15
0
0
20
15
25ns
Min
Max
35
35
35
3
0
0
25
0
0
20
20
35ns
Min
Max
45
45
45
3
0
0
30
20
45ns
Min
Max
55
55
55
55ns
Min
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE
(V
CC
= 5.0V, V
SS
= 0V, -55°C≤ T
A
≤
+125°C)
Symbol
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
JEDEC
t
AVAV
t
ELWH
t
ELEH
t
AVWL
t
AVEL
t
AVWH
t
AVEH
t
WLWH
t
WLEH
t
WHAX
t
EHAX
t
WHDX
t
EHDX
t
WLQZ
t
DVWH
t
DVEH
t
WHQX
Alt.
t
WC
t
CW
t
CW
t
AS
t
AS
t
AW
t
AW
t
WP
t
WP
t
WR
t
WR
t
DH
t
DH
t
WHZ
t
DW
t
DW
t
WLZ
15
13
13
0
0
13
13
13
13
0
0
0
0
0
8
8
0
8
15ns
Min
Max
17
14
14
0
0
14
14
14
14
0
0
0
0
0
8
8
0
8
17ns
Min
Max
20
15
15
0
0
15
15
15
15
0
0
0
0
0
10
10
0
8
20ns
Min
Max
25
17
17
0
0
17
17
17
17
0
0
0
0
0
12
12
0
10
25ns
Min
Max
35
25
25
0
0
25
25
25
25
0
0
0
0
0
20
20
0
25
35ns
Min
Max
45
30
30
0
0
30
30
30
30
0
0
0
0
0
25
25
0
30
45ns
Min
Max
55
50
50
0
0
50
50
45
45
0
0
0
0
0
40
30
0
30
55ns
Min
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 15
© 2014 Microsemi Corporation. All rights reserved.
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA
FIGURE 2 – TIMING WAVEFORM – READ CYCLE
t
AVAV
ADDRESS
t
AVAV
ADDRESS
ADDRESS 1
ADDRESS 2
t
AVQV
CS#
t
AVQV
DATA I/O
t
AVQX
OE#
DATA 1
DATA 2
t
ELQV
t
ELQX
t
GLQV
t
GLQX
DATA OUT
t
EHQZ
t
GHQZ
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
READ CYCLE 2 (WE# HIGH)
FIGURE 3 – WRITE CYCLE – WE# CONTROLLED
t
AVAV
ADDRESS
t
AVWH
t
ELWH
CS#
t
WHAX
t
AVWL
WE#
t
WLWH
t
DVWH
t
WHDX
DATA IN
DATA VALID
t
WLQZ
DATA OUT
HIGH Z
t
WHQX
WRITE CYCLE 1, WE# CONTROLLED
FIGURE 4 – WRITE CYCLE – CS# CONTROLLED
t
AVAV
ADDRESS
t
AVEH
t
ELEH
CS#
t
EHAX
t
AVEL
WE#
t
WLEH
t
DVEH
t
EHDX
DATA IN
DATA OUT
HIGH Z
DATA VALID
WRITE CYCLE 2, CS# CONTROLLED
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 15
© 2014 Microsemi Corporation. All rights reserved.
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA
DATA RETENTION CHARACTERISTICS (EDI88512LPA ONLY)
(-55°C
≤
T
A
≤
+125°C)
Characteristic
Low Power Version only
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time
Operation Recovery Time
Sym
V
CC
I
CCDR
t
CDR
T
R
Conditions
V
CC
= 2.0V
CS#
V
CC
-0.2V
V
IN
V
CC
-0.2V
or V
IN
0.2V
Min
2
–
0
t
AVAV
Typ
–
–
–
–
Max
–
2
–
–
Units
V
mA
ns
ns
FIGURE 5 – DATA RETENTION – CS# CONTROLLED
DATA RETENTION MODE
V
CC
t
CDR
CS#
CS# = V
CC
-0.2V
4.5V
V
CC
4.5V
t
R
DATA RETENTION, CS# CONTROLLED
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 15
© 2014 Microsemi Corporation. All rights reserved.
5
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
