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EDI8G32128V10MMC

SRAM Module, 128KX32, 10ns, CMOS, SIMM-64

器件类别:存储    存储   

厂商名称:Microsemi

厂商官网:https://www.microsemi.com

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器件参数
参数名称
属性值
是否Rohs认证
不符合
Objectid
1924495339
包装说明
SIMM-64
Reach Compliance Code
unknown
最长访问时间
10 ns
JESD-30 代码
R-XSMA-N64
内存密度
4194304 bit
内存集成电路类型
SRAM MODULE
内存宽度
32
功能数量
1
端子数量
64
字数
131072 words
字数代码
128000
工作模式
ASYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
128KX32
封装主体材料
UNSPECIFIED
封装形状
RECTANGULAR
封装形式
MICROELECTRONIC ASSEMBLY
并行/串行
PARALLEL
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
3 V
标称供电电压 (Vsup)
3.3 V
表面贴装
NO
技术
CMOS
温度等级
COMMERCIAL
端子形式
NO LEAD
端子位置
SINGLE
处于峰值回流温度下的最长时间
NOT SPECIFIED
文档预览
EDI8F32128V
128K x 32 Static RAM CMOS, High Speed Module
FEATURES
• 128K x 32 bit CMOS Static RAM
• Access Times: 10 and 12ns
• Individual Byte Selects
• Fully Static, No Clocks
• TTL Compatible I/O
• High Density Package
• JEDEC Standard Pinouts
• 64 Pad SIMM, No. 38
• 64 Pin ZIP, No. 39
• Common Data Inputs and Outputs
• Single +3.3V (±10%) Supply Operation
DESCRIPTION
The EDI8F32128V is a high speed 4 megabit Static RAM module
organized as 128K words by 32 bits. This module is constructed
from four 128K x 8 Static RAMs in SOJ packages on an epoxy
laminate (FR4) board.
Four chip enables (EØ-E3) are used to independently enable the
four bytes. Reading or writing can be executed on individual bytes
or any combination of multiple bytes through proper use of
enables.
The EDI8F32128V is offered in 64 pin ZIP and 64 Pad SIMM
packages, which enable four megabits of memory to be placed in
less than 1.3 square inches of board space.
All inputs and outputs are TTL compatible and operate from a
single 5V supply. Fully asynchronous circuitry requires no clocks
or refreshing for operation and provides equal access and cycle
times for ease of use.
Two pins, PD1 and PD2, are used to identify module memory
density in applications where alternate modules can be inter-
changed.
FIG. 1
PIN CONFIGURATIONS AND BLOCK DIAGRAM
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
VSS
PD2
DQ8
DQ9
DQ10
DQ11
A0
A1
A2
DQ12
DQ13
DQ14
DQ15
VSS
A15
E1
E3
NC
G
DQ24
DQ25
DQ26
DQ27
A3
A4
A5
VCC
A6
DQ28
DQ29
DQ30
DQ31
8F32128V Pin Conf
PIN NAMES
AØ-A16
Address Inputs
Chip Enables
Write Enable
Output Enable
Common Data Input/Output
Power (+3.3V±10%)
Ground
No Connection
EØ-E3
W
G
DQØ-DQ31
VCC
VSS
PD1
DQ0
DQ1
DQ2
DQ3
VCC
A7
A8
A9
DQ4
DQ5
DQ6
DQ7
W
A14
E0
E2
A16
VSS
DQ16
DQ17
DQ18
DQ19
A10
A11
A12
A13
DQ20
DQ21
DQ22
DQ23
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
A
0-16
W
G
17
128K x 8
8
DQ
0-7
E
0
128K x 8
8
DQ
8-15
NC
E
1
128K x 8
8
DQ
16-23
E
2
128K x 8
8
DQ
24-31
PD1 = Open
PD2 = Open
E
3
8F32128V Blk Dia
Aug, 2001 Rev. 0
ECO # 14560
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI8F32128V
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial
Storage Temperature
Power Dissipation
Output Current.
-0.5V to 4.6V
0°C to +70°C
-55°C to +125°C
2.5 Watts
20 mA
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Sym
VCC
VSS
VIH
VIL
Min
3.0
0
2.2
-0.3
Typ
3.3
0
--
--
Max
3.6
0
Vcc +0.3
0.8
Units
V
V
V
V
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Note:
For T
EHQZ
,T
GHQZ
and T
WLQZ
, CL = 5pF.
VSS to 3.0V
3ns
1.5V
1TTL, CL = 30pF
DC ELECTRICAL CHARACTERISTICS
Parameter
Operating Power
Supply Current
Standby (TTL) Power
Supply Current
Full Standby Power
Supply Current CMOS
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
*Typical: TA = 25°C, VCC = 5.0V
Sym
ICC1
ICC2
ICC3
ILI
ILO
VOH
VOL
Conditions
W, E = VIL, II/O = 0mA,
Min Cycle
E
³
VIH, VIN
£
VIL or
VIN
³
VIH
E
³
VCC - 0.2V
VIN
³
VCC - 0.2V or VIN
£
0.2V
VIN = 0V to VCC
V I/O = 0V to VCC
IOH = -4.0mA
IOL = 8.0mA
Min
Max
12-25ns
480
120
40
±20
±20
--
0.4
Units
mA
mA
mA
µA
µA
V
V
2.4
--
TRUTH TABLE
E
H
L
L
L
W
X
H
L
H
G
X
L
X
H
Mode
Standby
Read
Write
Output
Deselect
Output
HIGH Z
DOUT
DIN
HIGH Z
Power
ICC2/ICC3
ICC1
ICC1
ICC1
CAPACITANCE
(F=1.0MHZ, VIN=VCC OR VSS)
Parameter
Address Lines
Data Lines
Chip Enable Line
Write Line
Sym
CI
CD/Q
CC
CN
Max
45
20
20
45
Unit
pF
pF
pF
pF
These parameters are sampled, not 100% tested.
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
2
Aug. 2001 Rev. 0
ECO # 14560
EDI8F32128V
AC CHARACTERISTICS READ CYCLE
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Note 1: Parameter guaranteed, but not tested.
Symbol
JEDEC
Alt.
TAVAV
TRC
TAVQV
TAA
TELQV
TACS
TELQX
TCLZ
TEHQZ
TCHZ
TAVQX
TOH
TGLQV
TOE
TGLQX
TOLZ
TGHQZ
TOHZ
10ns
Min Max
10
10
10
3
5
3
5
0
5
12ns
Min Max
12
12
12
3
6
3
5
0
6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
FIG. 2
READ CYCLE 1 - W HIGH, G, E LOW
TAVAV
A
ADDRESS 1
TAVQV
Q
8F32128V Rd Cyc1
ADDRESS 2
TAVQX
DATA 1
DATA 2
FIG. 3
READ CYCLE 2 - W HIGH
TAVAV
A
TAVQV
E
TELQV
TELQX
G
TGLQV
TGLQX
Q
8F32128V Rd Cyc2
TEHQZ
TGHQZ
Aug, 2001 Rev. 0
ECO # 14560
3
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI8F32128V
AC CHARACTERISTICS WRITE CYCLE
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
Note 1: Parameter guaranteed, but not tested.
Symbol
JEDEC
Alt.
TAVAV
TWC
TELWH
TCW
TWLEH
TCW
TAVWL
TAS
TAVEL
TAS
TAVWH
TAW
TAVEH
TAW
TWLWH
TWP
TELEH
TWP
TWHAX
TWR
TEHAX
TWR
TWHDX
TDH
TEHDX
TDH
TWLQZ
TWHZ
TDVWH
TDW
TDVEH
TDW
TWHQX
TWLZ
10ns
Min Max
10
7
7
0
0
7
7
7
7
0
0
0
0
0
5
5
5
3
12ns
Min Max
12
8
8
0
0
8
8
8
8
0
0
0
0
0
6
6
6
3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FIG. 4
WRITE CYCLE 1 - W CONTROLLED
TAVAV
A
E
TELWH
TAVWH
TWLWH
W
D
TWLQZ
Q
8F32128C Write Cyc1
TWHAX
TAVWL
TDVWH
TWHDX
TWHQX
HIGH Z
DATA VALID
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
4
Aug. 2001 Rev. 0
ECO # 14560
EDI8F32128V
FIG. 5
WRITE CYCLE 2 - E CONTROLLED
TAVAV
A
TAVEL
E
TAVEH
TWLEH
W
TDVEH
D
Q
8F32128V Write Cyc2
TELEH
TEHAX
TEHDX
DATA VALID
HIGH Z
Aug, 2001 Rev. 0
ECO # 14560
5
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
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