DATA SHEET
256M bits SDRAM
EDS2516APTA (16M words
×
16 bits)
Description
The EDS2516AP is a 256M bits SDRAM organized as
4,194,304 words
×
16 bits
×
4 banks. All inputs and
outputs are referred to the rising edge of the clock
input. It is packaged in standard 54-pin plastic TSOP
(II)
Pin Configurations
/xxx indicates active low signal.
54-pin plastic TSOP (II)
VDD
DQ0
VDDQ
Features
•
•
•
•
•
•
DQ1
DQ2
VSSQ
3.3V power supply
Clock frequency: 166MHz/133MHz (max.)
LVTTL interface
Single pulsed /RAS
×16
organization
4 banks can operate simultaneously and
independently
•
Burst read/write operation and burst read/single write
operation capability
•
Programmable burst length (BL): 1, 2, 4, 8, full page
•
2 variations of burst sequence
⎯
Sequential (BL = 1, 2, 4, 8, full page)
⎯
Interleave (BL = 1, 2, 4, 8)
•
Programmable /CAS latency (CL): 2, 3
•
Byte control by UDQM and LDQM
Refresh cycles: 8192 refresh cycles/64ms
•
2 variations of refresh
⎯
Auto refresh
⎯
Self refresh
•
2 types of TSOP (II) package
⎯
Sn-Pb solder
⎯
Lead free solder (Sn-Bi)
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
EO
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Document No. E0359E20 (Ver. 2.0)
Date Published January 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida
Memory, Inc. 2003-2005
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A0 to A12,
BA0, BA1
(Top view)
UDQM,LDQM
Input/output mask
Address input
Bank select address
DQ0 to DQ15
Data-input/output
Chip select
/CS
Row address strobe
/RAS
Column address strobe
/CAS
Write enable
/WE
CKE
CLK
VDD
VSS
VDDQ
VSSQ
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
NC
Power for DQ circuit
Ground for DQ circuit
No connection
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EDS2516APTA
Ordering Information
Part number
EDS2516APTA-60*
EDS2516APTA-7A
EDS2516APTA-75*
2
EDS2516APTA-60L*
1
EDS2516APTA-7AL
EDS2516APTA-75L*
2
EDS2516APTA-60-E*
1
EDS2516APTA-7A-E
EDS2516APTA-75-E*
2
EDS2516APTA-60L-E*
1
EDS2516APTA-7AL-E
EDS2516APTA-75L-E*
2
P
16M
×
16
4
1
Mask
Version
P
Organization
(words
×
bits)
16M
×
16
Internal Banks
4
Clock frequency
MHz (max.)
166
133
133
166
133
133
166
133
133
166
133
133
/CAS latency Package
3
2, 3
3
3
2, 3
3
3
2, 3
3
3
2, 3
3
54-pin Plastic
TSOP (II)
54-pin Plastic
TSOP (II) (lead-free)
EO
Part Number
Elpida Memory
Type
D: Monolithic Device
Product Family
S: SDRAM
Density / Bank
25: 256M / 4bank
Organization
16: x16
Power Suppiy, Interface
A: 3.3V, LVTTL
Die Rev.
Package
TA: TSOP (II)
Speed
60: 166MHz/CL3
133MHz/CL2
7A: 133MHz/CL2, 3
75: 133MHz/CL3
100MHz/CL2
Spec.Detail
Blank: Normal
L: Low Power
Environment Code
Blank: Sn-Pb Solder
E: Lead Free
Data Sheet E0359E20 (Ver. 2.0)
Notes: 1. 133MHz operation at /CAS latency = 2.
2. 100MHz operation at /CAS latency = 2.
E D S 25 16 A P TA - 7A L - E
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EDS2516APTA
CONTENTS
Description .................................................................................................................................................... 1
Features ........................................................................................................................................................ 1
Pin Configurations......................................................................................................................................... 1
Ordering Information ..................................................................................................................................... 2
Part Number.................................................................................................................................................. 2
Electrical Specifications ................................................................................................................................ 4
Block Diagram............................................................................................................................................. 13
Pin Function ................................................................................................................................................ 14
Command Operation................................................................................................................................... 16
Simplified State Diagram ............................................................................................................................ 24
Mode Register Configuration ...................................................................................................................... 25
Power-up sequence .................................................................................................................................... 27
Operation of the SDRAM ............................................................................................................................ 28
Timing Waveforms ...................................................................................................................................... 44
Package Drawing........................................................................................................................................ 50
Recommended Soldering Conditions ......................................................................................................... 51
EO
Data Sheet E0359E20 (Ver. 2.0)
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EDS2516APTA
Electrical Specifications
•
All voltages are referenced to VSS (GND).
•
After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating temperature
Symbol
VT
VDD
IOS
PD
TA
Tstg
Rating
–0.5 to VDD + 0.5 (≤ 4.6 (max.))
–0.5 to +4.6
50
1.0
0 to +70
–55 to +125
Unit
V
V
mA
W
°C
°C
Note
EO
Storage temperature
Parameter
Supply voltage
Input high voltage
Input low voltage
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions (TA = 0 to +70°C)
Symbol
VDD, VDDQ
min.
3.0
0
2.0
–0.3
max.
3.6
0
VDD + 0.3
0.8
Unit
V
V
V
V
Notes
1
2
3
4
L
VSS, VSSQ
VIH
VIL
Notes: 1.
2.
3.
4.
The supply voltage with all VDD and VDDQ pins must be on the same level.
The supply voltage with all VSS and VSSQ pins must be on the same level.
VIH (max.) = VDD + 2.0 V for pulse width
≤
3ns at VDD.
VIL (min.) = VSS – 2.0 V for pulse width
≤
3ns at VSS.
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Data Sheet E0359E20 (Ver. 2.0)
EDS2516APTA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Operating current
Standby current in power down
Standby current in power down
(input signal stable)
Symbol
ICC1
ICC2P
ICC2PS
Grade
-60, -7A
-75
max.
135
115
3
2
20
9
4
3
30
15
-60
-7A, -75
-60, -7A
-75
180
145
250
220
3
-XXL
1
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Test condition
Burst length = 1
tRC = tRC (min.)
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
∞,
/CS = VIH
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
∞,
/CS = VIH
tCK = tCK (min.),
BL = 4
tRC = tRC (min.)
VIH
≥
VDD – 0.2V
VIL
≤
0.2V
VIH
≥
VDD – 0.2V
VIL
≤
0.2V
Notes
1, 2, 3
6
7
4
8
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
3
Standby current in non power down ICC2N
Standby current in non power down
(input signal stable)
Active standby current in power
down
Active standby current in power
down (input signal stable)
Active standby current in non
power down
Active standby current in non
power down (input signal stable)
Burst operating current
Refresh current
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
ICC5
EO
Self refresh current
Self refresh current
(L-version)
Data Sheet E0359E20 (Ver. 2.0)
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
L
ICC6
ICC6
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