PRELIMINARY DATA SHEET
256M bits SDRAM
EDS2732CABB (8M words
×
32 bits)
Description
The EDS2732CA is a 256M bits SDRAM organized as
2,097,152 words
×
32 bits
×
4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
It is packaged in 90-ball FBGA.
Pin Configurations
/xxx indicate active low signal.
90-ball FBGA
1
2
3
4
5
6
7
8
9
A
DQ26 DQ24 VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC
A2
A10
NC
BA0
/CAS
VDD
DQ6
DQ1
DQ16 VSSQ
DQM2 VDD
A0
BA1
/CS
A1
A11
/RAS
Features
•
•
•
•
•
2.5V power supply
Clock frequency: 133MHz/100MHz (max.)
Single pulsed /RAS
×32
organization
4 banks can operate simultaneously and
independently
•
Burst read/write operation and burst read/single write
operation capability
•
Programmable burst length (BL): 1, 2, 4, 8 and full
page
•
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
•
Programmable /CAS latency (CL): 2, 3
•
Byte control by DQM
•
Address
8K Row address /256 column address
•
Refresh cycles
4096 refresh cycles/64ms
•
2 variations of refresh
Auto refresh
Self refresh
•
FBGA package is lead free solder (Sn-Ag-Cu)
B
DQ28 VDDQ VSSQ
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31
NC
A3
A6
A12
A9
NC
VSS
F
VSS DQM3
G
A4
A5
A8
CKE
NC
H
A7
J
CLK
K
DQM1
/WE DQM0
DQ7 VSSQ
DQ5 VDDQ
DQ3 VDDQ
L
VDDQ DQ8
M
VSSQ DQ10 DQ9
N
VSSQ DQ12 DQ14
P
DQ11 VDDQ VSSQ
VDDQ VSSQ DQ4
VDD
DQ0
DQ2
R
DQ13 DQ15 VSS
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0372E10 (Ver. 1.0)
Date Published April 2003 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2003
EDS2732CABB
Ordering Information
Part number
EDS2732CABB-75-E
EDS2732CABB-1A-E
EDS2732CABB-75L-E
EDS2732CABB-1AL-E
Supply
voltage
2.5V
Organization
(words
×
bits) Internal Banks
8M
×
32
4
Clock frequency
MHz (max.)
133
100
100
133
100
100
/CAS latency
3
2
2, 3
3
2
2, 3
Package
90-ball FBGA
Part Number
E D S 27 32 C A BB - 75 L - E
Elpida Memory
Type
D: Monolithic Device
Environment Code
Blank: Sn-Pb Solder
E: Lead Free
Power Consumption
Blank: Normal
L: Low Power
Speed
75: 133MHz/CL3
100MHz/CL2
1A: 100MHz/CL2,CL3
Package
BB: FBGA
Product Code
S: SDRAM
Density / Bank
27: 256M/4-Bank, 8K Rows
Bit Organization
32: x32
Voltage, Interface
C: 2.5V, LVTTL
Die Rev.
Preliminary Data Sheet E0372E10 (Ver. 1.0)
2
EDS2732CABB
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram ...............................................................................................................................................9
Pin Function.................................................................................................................................................10
Command Operation ...................................................................................................................................11
Simplified State Diagram .............................................................................................................................19
Mode Register Configuration.......................................................................................................................20
Power-up sequence.....................................................................................................................................22
Operation of the SDRAM.............................................................................................................................23
Timing Waveforms.......................................................................................................................................39
Package Drawing ........................................................................................................................................45
Recommended Soldering Conditions ..........................................................................................................46
Preliminary Data Sheet E0372E10 (Ver. 1.0)
3
EDS2732CABB
Electrical Specifications
•
All voltages are referenced to VSS (GND).
•
After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
Symbol
VT
VDD
IOS
PD
TA
Tstg
Rating
–0.5 to +3.6
–0.5 to +3.6
50
1.0
0 to +70
–55 to +125
Unit
V
V
mA
W
°C
°C
Note
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70°C)
°
Parameter
Supply voltage
Input high voltage
Input low voltage
Symbol
VDD, VDDQ
VSS, VSSQ
VIH
VIL
min.
2.3
0
1.7
–0.3
max.
2.7
0
VDD + 0.3
0.7
Unit
V
V
V
V
Notes
1
2
3
4
Notes: 1.
2.
3.
4.
The supply voltage with all VDD and VDDQ pins must be on the same level.
The supply voltage with all VSS and VSSQ pins must be on the same level.
VIH (max.) = VDD + 1.5V (pulse width
≤
5ns).
VIL (min.) = VSS – 1.5V (pulse width
≤
5ns).
Preliminary Data Sheet E0372E10 (Ver. 1.0)
4
EDS2732CABB
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
°
Parameter
/CAS latency
Operating current
Standby current in power down
Standby current in power down
(input signal stable)
Standby current in non power
down
Standby current in non power
down (input signal stable)
Active standby current in power
down
Active standby current in power
down (input signal stable)
Active standby current in non
power down
Active standby current in non
power down (input signal stable)
Burst operating current
Refresh current
Self refresh current
Self refresh current
(L-version)
Symbol
IDD1
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
IDD3PS
IDD3N
IDD3NS
IDD4
IDD5
IDD6
IDD6
-XXL
-75
-1A
-75
-1A
Grade
max.
105
3
2
20
9
4
3
50
30
155
125
265
255
3
1
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Test condition
Burst length = 1
tRC = tRC (min.)
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
∞,
/CS = VIH
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
∞,
/CS = VIH
tCK = tCK (min.),
BL = 4
tRC = tRC (min.)
VIH
≥
VDD – 0.2V
VIL
≤
0.2V
VIH
≥
VDD – 0.2V
VIL
≤
0.2V
Notes
1, 2, 3
6
7
4
8
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
3
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Preliminary Data Sheet E0372E10 (Ver. 1.0)
5
