EH1420SJETTTS-70.656M TR
Series
RoHS Compliant 5.0V Plastic J-Lead SMD HCMOS/TTL
High Frequency Oscillator
Frequency Tolerance/Stability
±20ppm Maximum
Package
Operating Temperature Range
-40°C to +85°C
RoHS
EH14 20 SJ ET T TS -70.656M TR
Packaging Options
Tape & Reel
Nominal Frequency
70.656MHz
Pin 1 Connection
Tri-State (Disabled Output: High Impedance)
Duty Cycle
50 ±5(%)
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
70.656MHz
±20ppm Maximum (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the
Operating Temperature Range, Supply Voltage Change, Output Load Change, 1st Year Aging at 25°C,
Shock, and Vibration)
±5ppm/year Maximum
-40°C to +85°C
5.0Vdc ±10%
50mA Maximum (No Load)
2.4Vdc Minimum with TTL Load, Vdd-0.4Vdc Minimum with HCMOS Load, IOH = -16mA
0.4Vdc Maximum with TTL Load, 0.5Vdc Maximum with HCMOS Load, IOL = +16mA
4nSec Maximum (Measured at 0.8Vdc to 2.0Vdc with TTL Load; Measured at 20% to 80% of waveform
with HCMOS Load)
50 ±5(%) (Measured at 50% of waveform with TTL Load or with HCMOS Load)
5TTL Load or 15pF HCMOS Load Maximum
CMOS
Tri-State (Disabled Output: High Impedance)
+2.2Vdc Minimum to enable output, +0.8Vdc Maximum to disable output (High Impedance), No Connect to
enable output.
±250pSec Maximum, ±100pSec Typical
±50pSec Maximum, ±30pSec Typical
10mSec Maximum
-55°C to +125°C
Aging at 25°C
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Pin 1 Connection
Tri-State Input Voltage (Vih and Vil)
Absolute Clock Jitter
One Sigma Clock Period Jitter
Start Up Time
Storage Temperature Range
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
Fine Leak Test
Flammability
Gross Leak Test
Mechanical Shock
Moisture Resistance
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 3015, Class 1, HBM: 1500V
MIL-STD-883, Method 1014, Condition A (Internal Crystal Only)
UL94-V0
MIL-STD-883, Method 1014, Condition C (Internal Crystal Only)
MIL-STD-202, Method 213, Condition C
MIL-STD-883, Method 1004
MIL-STD-202, Method 210, Condition K
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010, Condtion B
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Rev E 3/12/2011 | Page 1 of 6
EH1420SJETTTS-70.656M TR
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
5.080
±0.203
1
0.25 MIN
2
4
7.620
±0.203
9.8
MAX
3
3
4
MARKING
ORIENTATION
1
2
14.0
MAX
CONNECTION
Tri-State (High
Impedance)
Ground
Output
Supply Voltage
LINE MARKING
1
ECLIPTEK
70.656M
XXXXXX
XXXXXX=Ecliptek
Manufacturing Identifier
2
3
0.510 ±0.203
4.7
MAX
Suggested Solder Pad Layout
All Dimensions in Millimeters
1.27 (X4)
3.0 (X4)
5.8
Solder Land
(X4)
3.81
All Tolerances are ±0.1
www.ecliptek.com | Specification Subject to Change Without Notice | Rev E 3/12/2011 | Page 2 of 6
EH1420SJETTTS-70.656M TR
OUTPUT WAVEFORM & TIMING DIAGRAM
TRI-STATE INPUT
V
IH
V
IL
CLOCK OUTPUT
V
OH
80% or 2.0V
DC
50% or 1.4V
DC
20% or 0.8V
DC
V
OL
OUTPUT DISABLE
(HIGH IMPEDANCE
STATE)
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
Test Circuit for TTL Output
Output Load
Drive Capability
10TTL
5TTL
2TTL
10LSTTL
1TTL
R
L
Value
(Ohms)
390
780
1100
2000
2200
C
L
Value
(pF)
15
15
6
15
3
Oscilloscope
Frequency
Counter
Table 1: R
L
Resistance Value and C
L
Capacitance
Value Vs. Output Load Drive Capability
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
R
L
(Note 4)
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
+
0.01µF
(Note 1)
0.1µF
(Note 1)
C
L
(Note 3)
Power
Supply
_
Ground
No Connect
or Tri-State
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and V
DD
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
Note 4: Resistance value R
L
is shown in Table 1. See applicable specification sheet for 'Load Drive Capability'.
Note 5: All diodes are MMBD7000, MMBD914, or equivalent.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev E 3/12/2011 | Page 3 of 6
EH1420SJETTTS-70.656M TR
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.01µF
(Note 1)
0.1µF
(Note 1)
Ground
C
L
(Note 3)
No Connect
or Tri-State
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and V
DD
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev E 3/12/2011 | Page 4 of 6
EH1420SJETTTS-70.656M TR
Tape & Reel Dimensions
Quantity Per Reel: 1,000 units
4.0 ±0.2
2.0 ±0.1
1.5 +1.0/-0.0
0.3 ±0.1
11.5 ±0.1
24.0 ±0.3
10.75 ±0.10
A0*
12.0 ±0.1
*Compliant to EIA 481A
B0*
K0*
1.5 MIN
DIA 40 MIN
Access Hole at
Slot Location
30.4 MAX
360 MAX
DIA 50 MIN
DIA 20.2 MIN
2.5 MIN Width
10.0 MIN Depth
Tape slot in Core
for Tape Start
24.4 +2.0/-0.0
DIA 13.0 ±0.2
www.ecliptek.com | Specification Subject to Change Without Notice | Rev E 3/12/2011 | Page 5 of 6
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