16Mb SDRAM
Ordering Information
EM 48 1M 16 2 2 V T A – 6 L
EOREX
Memory
EDO/FPM
D-RAMBUS
DDRSDRAM
DDRSGRAM
SGRAM
SDRAM
Density
16M
: 16 Mega Bits
8M
: 8 Mega Bits
4M
: 4 Mega Bits
2M
: 2 Mega Bits
1M
: 1 Mega Bit
:
:
:
:
:
:
40
41
42
43
46
48
Power
Blank : Standard
L
: Low power
I
: Industrial
F:
PB free package
Organization
8
: x8
9
: x9
16
: x16
18
: x18
32
: x32
Refresh
1
: 1K,
8
: 8K
2
: 2K,
6
:16K
4
: 4K
Bank
2
: 2Bank
6
: 16Bank
4
: 4Bank
3
: 32Bank
8
: 8Bank
Min Cycle Time ( Max Freq.)
-5
: 5ns ( 200MHz )
-6
: 6ns ( 167MHz )
-7
: 7ns ( 143MHz )
-75
: 7.5ns ( 133MHz )
-8
: 8ns ( 125MHz )
-10
: 10ns ( 100MHz )
Revision
A :
1st
B :
2nd
C :
3rd
D :4th
Interface
V:
3.3V
R:
2.5V
Package
C:
CSP
B:
uBGA
T:
TSOP
Q:
TQFP
P:
PQFP ( QFP )
1/18
Rev.01
16Mb SDRAM
16Mb ( 2Banks ) Synchronous DRAM
EM481M1622VTA (1Mx16)
Description
The EM481M1622VTA is Synchronous Dynamic Random Access Memory (SDRAM) organized as
512K x 2 banks x 16 bits. All inputs and outputs are synchronized with the positive edge of the clock.
The 16Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates
and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power
saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL
.
Feature
synchronous to positive clock edge
•
Single 3.3V +/- 0.3V power supply
• LVTTL compatible with multiplexed address
• Programmable Burst Length (B/ L) - 1,2,4,8 or full page
• Programmable CAS Latency (C/ L) - 2 or 3
• Data Mask (DQM) for Read / Write masking
• Programmable wrap sequence - Sequential ( B/ L = 1/2/4/8/full page )
- Interleave ( B/ L = 1/2/4/8 )
• Burst read with single-bit write operation
• All inputs are sampled at the rising edge of the system clock.
• Auto refresh and self refresh
• 2,048 refresh cycles / 32ms
•
Fully
* EOREX reserves the right to change products or specification without notice.
2/18
Rev.01
16Mb SDRAM
Pin Assignment ( Top View )
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
/WE
/CAS
/RAS
/CS
BA
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
50pin TSOP-II
3/18
Rev.01
16Mb SDRAM
Pin Descriptions ( Simplified )
Pin
CLK
/CS
CKE
Name
System Clock
Chip select
Clock Enable
Pin Function
Master Clock Input(Active on the Positive rising edge)
Selects chip when active
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
Row address (A0 to A10) is determined by A0 to A10 level
at the bank active command cycle CLK rising edge.
CA(CA0 to CA7) is determined by A0 to A7 level at the
read or write command cycle CLK rising edge.
And this column address becomes burst access start
address. A10 defines the pre-charge mode. When A10 = High
at the pre-charge command cycle, all banks are pre-charged.
But when A10 = Low at the pre-charge command cycle,
only the bank that is selected by BA is pre-charged.
Selects which bank is to be active.
Latches Row Addresses on the positive rising edge of the
CLK with /RAS “L”. Enables row access & pre-charge.
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
A0 ~ A10
Address
BA
Bank Address
/RAS
Row address strobe
/CAS
Column address strobe
/WE
Write Enable
UDQM /LDQM
Data input/output Mask
DQM controls I/O buffers.
DQ0 ~ 15
Data input/output
DQ pins have the same function as I/O pins on a conventional
DRAM.
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Power supply/Ground
Power supply/Ground
No connection
V
DD
and V
SS
are power supply pins for internal circuits.
V
DDQ
and V
SSQ
are power supply pins for the output buffers.
This pin is recommended to be left No Connection on the
device.
4/18
Rev.01
16Mb SDRAM
Block Diagram
A0
A1
A2
Row Add. Buffer
Auto/Self
Refresh Counter
DQM
Address Register
Row Decoder
A3
A4
A5
A6
A7
A8
A9
A10
BA
Memory
Array
S/A & I/O gating
Col. Decoder
Col. Add. Buffer
Write DQM
Control
Data In
DQi
Data Out
Read DQM
Control
Mode Register Set
Col. Add. Counter
Burst Counter
DQM
/WE
DQM
Timing Register
CLK
CKE
/CS
/RAS
/CAS
5/18
Rev.01
