eorex
Features
Preliminary
EM42BM1684LBB
512Mb (8M
×
4Bank
×
16)
Double DATA RATE SDRAM
Description
The EM42BM1684LBB is high speed Synchronous
graphic RAM fabricated with ultra high performance
CMOS process containing 536,870,912 bits which
organized as 8Meg words x 4 banks by 16 bits.
The 512Mb DDR SDRAM uses a double data rate
architecture to accomplish high-speed operation.
The data path internally prefetches multiple bits and
It transfers the datafor both rising and falling edges
of the system clock.It means the doubled data
bandwidth can be achieved at the I/O pins.
Available packages:FBGA-60B(11.5mmx10mm).
• Internal Double-Date-Rate architecture with 2
Accesses per clock cycle.
• 1.8V
±0.1V
VDD/VDDQ
• 1.8V LV-COMS compatible I/O
• Burst Length (B/L) of 2, 4, 8, 16
• 3 Clock read latency (CL3)
• Bi-directional,intermittent data strobe(DQS)
• All inputs except data and DM are sampled
at the positive edge of the system clock.
• Data Mask (DM) for write data
• Sequential & Interleaved Burst type available
• Auto Precharge option for each burst accesses
• DQS edge-aligned with data for Read cycles
• DQS center-aligned with data for Write cycles
• No DLL;CK to DQS is not synchronized
• Deep power down mode
• Partial Array Self-Refresh(PASR)
• Auto Temperature Compensated Self-Refresh
(TCSR) by built-in temperature sensor
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
Ordering Information
Part No
EM42BM1684LBB-75F
EM42BM1684LBB-75FE
Organization
32M X 16
32M X 16
Max. Freq
133MHz/DDR266 @CL3
133MHz/DDR266 @CL3
Package
BGA-60B
BGA-60B
Grade
Commercial.
Extend Temp.
Pb
Free
Free
* EOREX reserves the right to change products or specification without notice.
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1/20
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Pin Assignment
1
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CKE
A9
A6
VSS
2
DQ15
DQ13
DQ11
DQ9
UDQS
UDM
CLK
A11
A7
A4
Preliminary
EM42BM1684LBB
3
VSSQ
DQ14
DQ12
DQ10
DQ8
NC
/CLK
A12
A8
A5
A
B
C
D
E
F
G
H
J
K
7
VDDQ
DQ1
DQ3
DQ5
DQ7
NC
/WE
/CS
A10/AP
A2
8
DQ0
DQ2
DQ4
DQ6
LDQS
LDM
/CAS
BA0
A0
A3
9
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VDD
/RAS
BA1
A1
VDD
60ball FBGA / (11.5mm x 10mm x 1mm)
Jul. 2006
2/20
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Pin
Name
G2,G3
CLK,/CLK
Preliminary
EM42BM1684LBB
Pin Description (Simplified)
Function
(System Clock)
Clock input active on the Positive rising edge except for DQ and
DM are active on both edge of the DQS.
CLK and /CLK are differential clock inputs.
(Chip Select)
/CS enables the command decoder when ”L” and disable the
command decoder when “H”.The new command are over-
Looked when the command decoder is disabled but previous
operation will still continue.
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
When deactivate the clock,CKE low signifies the power down or
self refresh mode.
(Address)
Row address (A0 to A12) and Calumn address (CA0 to CA9) are
multiplexed on the same pin.
CA10 defines auto precharge at Calumn address.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK with
/RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
Latches Column Addresses on the positive rising edge of the CLK
with /CAS low. Enables column access.
(Write Enable)
Latches Column Addresses on the positive rising edge of the CLK
with /CAS low. Enables column access.
(Data Input/Output)
Data Inputs and Outputs are synchronized with both edge of DQS.
(Data Input/Output Mask)
DM controls data inputs.LDM corresponds to the data on
DQ0~DQ7.UDM corresponds to the data on DQ8~DQ15……..
(Data Input/Output)
Data inputs and outputs are multiplexed on the same pin.
(Power Supply/Ground)
V
DD
and V
SS
are power supply pins for internal circuits.
(Power Supply/Ground)
V
DDQ
and V
SSQ
are power supply pins for the output buffers.
(No Connection/Reserved for Future Use)
This pin is recommended to be left No Connection on the device.
H8
/CS
H1
CKE
K7,L8,L7,M8,M2,
L3,L2,K3,K2,J3,K8,
J2,H2
J8,J7
H7
A0~12
BA0, BA1
/RAS
G8
/CAS
G7
E7,E3
F7,F8
A8,B9,B7,C9
C7,D9,D7,E9
E1,D3,D1,C3
C1,B3,B1,A2
A7,F8,M7/
A3,F2,M3
A9,B1,C8,D2,E8 /
A1,B8,C2,D8,E2,
F1,F9
/WE
LDQS,
UDQS
LDM,UDM
DQ0~15
V
DD
/V
SS
V
DDQ
/V
SSQ
NC/RFU
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3/20
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Absolute Maximum Rating
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
OP
T
STG
P
D
Preliminary
EM42BM1684LBB
Item
Input, Output Voltage
Power Supply Voltage
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Rating
-0.5 ~ +2.3
-0.5 ~ +2.3
Commercial
0 ~ +70
Extended
-25 ~ +85
-55 ~ +125
1
Units
V
V
°C
°C
W
I
OS
Short Circuit Current
50
mA
Note:
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could
cause permanent damage. The device is not meant to be operated under conditions outside the
limits described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Capacitance (V
CC
=1.8V
±
0.1V, f=1MHz, T
A
=25°C)
Symbol
C
CLK
C
I
C
O
Parameter
Clock Capacitance
Input Capacitance for CLK, CKE, Address,
/CS, /RAS, /CAS, /WE, DQML, DQMU
Input/Output Capacitance
Min.
2.0
2.0
3.5
Typ.
Max.
4.5
4.5
6.0
Units
pF
pF
pF
Recommended DC Operating Conditions (T
A
=0°C ~70°C)
Symbol
V
DD
V
DDQ
V
IH
Parameter
Power Supply Voltage
Power Supply Voltage (for I/O Buffer)
Input Logic High Voltage
Min.
1.7
1.7
0.8* V
DDQ
-0.3
Typ.
1.8
1.8
Max.
1.9
1.9
V
DDQ
+0.3
0.2*V
DDQ
Units
V
V
V
V
V
IL
Input Logic Low Voltage
Note:
* All voltages referred to V
SS
.
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4/20
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(V
DD
=1.8V±0.1V, T
A
=0°C ~ 70°C)
Symbol
I
DD1
I
DD2P
Parameter
Operating Current
(Note 1)
Preliminary
EM42BM1684LBB
Recommended DC Operating Conditions
Max.
-75
70
1
Test Conditions
Burst length=2,
t
RC
≥t
RC
(min.), I
OL
=0mA,
One bank active
CKE≤V
IL
(max.), t
CK
=min
CKE≥V
IL
(min.), t
CK
=min,
/CS≥V
IH
(min.)
Input signals are changed one time
during 2 clks
CKE≤V
IL
(max.), t
CK
=min
CKE≥V
IH
(min.), t
CK
=min,
/CS≥V
IH
(min.)
Input signals are changed one time
during 2 clks
t
CK
≥
t
CK
(min.), I
OL
=0mA,
All banks active
t
RC
≥
t
RFC
(min.), All banks active
CKE≤0.2V
Units
mA
mA
Precharge Standby Current in
Power Down Mode
Precharge Standby Current in
Non-power Down Mode
Active Standby Current in
Power Down Mode
Active Standby Current in
Non-power Down Mode
Operating Current (Burst
(Note 2)
Mode)
Refresh Current
(Note 3)
I
DD2N
4
mA
I
DD3P
3
mA
I
DD3N
10
mA
I
DD4
I
DD5
I
DD6
140
100
0.8
mA
mA
mA
Self Refresh Current
*All voltages referenced to V
SS
.
Note 1:
I
DD1
depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during t
CK
(min.)
Note 2:
I
DD4
depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during t
CK
(min.)
Note 3:
Min. of t
RFC
(Auto refresh Row Cycle Times) is shown at AC Characteristics.
Recommended DC Operating Conditions (Continued)
Symbol
I
IL
I
OL
V
OH
V
OL
Parameter
Input Leakage Current
Output Leakage Current
High Level Output Voltage
Low Level Output Voltage
Test Conditions
0≤V
I
≤V
DDQ
, V
DDQ
=V
DD
All other pins not under
test=0V
0≤V
O
≤V
DDQ
, D
OUT
is disabled
I
O
=-0.1mA
I
O
=+0.1mA
Min.
-2
-1.5
0.9*V
DDQ
0.1*V
DDQ
Typ.
Max.
+2
+1.5
Units
uA
uA
V
V
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5/20
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