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Features
• Fully Synchronous to Positive Clock Edge
• Single 2.7V ~ 3.6V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms (7.8us)
EM48AM1684VBA
256Mb (4M
×
4Bank
×
16) Synchronous DRAM
Description
The EM48AM1684VBA is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
4Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 256Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages:TFBGA 54B 12mm x 8mm.
Ordering Information
Part No
EM48AM1684VBA-75F
Organization
16M X 16
Max. Freq
133MHz @CL3
Package
TFBGA -54B
Grade
Commercial
Pb
Free
* EOREX reserves the right to change products or specification without notice.
Jul. 2006
1/17
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Pin Assignment: TFBGA 54B
1
VSS
DQ14
DQ12
DQ10
DQ8
UDQM
A12
A8
VSS
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
2
3
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
A
B
C
D
E
F
G
H
J
EM48AM1684VBA
7
VDDQ
VSSQ
VDDQ
VSSQ
VDD
/CAS
BA0
A0
A3
DQ0
DQ2
DQ4
DQ6
8
VDD
DQ1
DQ3
DQ5
DQ7
/WE
/CS
A10
VDD
9
LDQM
/RAS
BA1
A1
A2
54ball TFBGA / (12mm
×
8mm)
Jul. 2006
2/17
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Pin Description (Simplified)
Pin
F2
G9
Name
CLK
/CS
EM48AM1684VBA
Function
(System Clock)
Master clock input (Active on the positive rising edge)
(Chip Select)
Selects chip when active
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
(Address)
Row address (A0 to A12) is determined by A0 to A12 level at
the bank active command cycle CLK rising edge.
CA (CA0 to CA8) is determined by A0 to A8 level at the read or
write command cycle CLK rising edge.
And this column address becomes burst access start address.
A10 defines the pre-charge mode. When A10= High at the
pre-charge command cycle, all banks are pre-charged.
But when A10= Low at the pre-charge command cycle, only the
bank that is selected by BA0/BA1 is pre-charged.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK
with /RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Write Enable)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Data Input/Output Mask)
DQM controls I/O buffers.
(Data Input/Output)
DQ pins have the same function as I/O pins on a conventional
DRAM.
(Power Supply/Ground)
V
DD
and V
SS
are power supply pins for internal circuits.
(Power Supply/Ground)
V
DDQ
and V
SSQ
are power supply pins for the output buffers.
(No Connection)
This pin is recommended to be left No Connection on the
device.
F3
CKE
H7,H8,J8,J7,J3,
J2,H3,H2,H1,G3,
H9,G2,G1
A0~A12
G7,G8
F8
BA0, BA1
/RAS
F7
/CAS
F9
F1/E8
A8,B9,B8,C9,C8,
D9,D8,E9,E1,D2,
D1,C2,C1,B2,B1,
A2
A9,E7,J9/
A1,E3,J1
A7,B3,C7,D3/
A3,B7,C3,D7
E2
/WE
UDQM/LDQM
DQ0~DQ15
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Jul. 2006
3/17
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Absolute Maximum Rating
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
OP
T
STG
P
D
Item
Input, Output Voltage
Power Supply Voltage
Operating Temperature Range
Storage Temperature Range
Power Dissipation
EM48AM1684VBA
Rating
-0.3 ~ +4.6
-0.3 ~ +4.6
Commercial
0 ~ +70
Extended
-25 ~ +85
-55 ~ +150
1
Units
V
V
°C
°C
W
I
OS
Short Circuit Current
50
mA
Note:
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could
cause permanent damage. The device is not meant to be operated under conditions outside the
limits described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Capacitance (V
CC
=3.3V, f=1MHz, T
A
=25°C)
Symbol
C
CLK
C
I
C
O
Parameter
Clock Capacitance
Input Capacitance for CLK, CKE, Address,
/CS, /RAS, /CAS, /WE, DQML, DQMU
Input/Output Capacitance
Min.
Typ.
Max.
3.5
3.8
6.0
Units
pF
pF
pF
Recommended DC Operating Conditions (T
A
=0°C ~+70°C)
Symbol
V
DD
V
DDQ
V
IH
Parameter
Power Supply Voltage
Power Supply Voltage (for I/O Buffer)
Input Logic High Voltage
Min.
2.7
2.7
2.0
-0.3
Typ.
3.3
3.3
Max.
3.6
3.6
V
DD
+0.3
0.8
Units
V
V
V
V
V
IL
Input Logic Low Voltage
Note:
* All voltages referred to V
SS
.
* V
IH
(max.) = 5.6V for pulse width 3ns
* V
IL
(min.) = -2.0V for pulse width 3ns
Jul. 2006
4/17
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Recommended DC Operating Conditions
(V
DD
=3.3V±0.3V, T
A
=0°C ~ 70°C)
Symbol
I
CC1
I
CC2P
I
CC2PS
I
CC2N
Parameter
Operating Current
(Note 1)
EM48AM1684VBA
Test Conditions
Burst length=1,
t
RC
≥t
RC
(min.), I
OL
=0mA,
One bank active
CKE≤V
IL
(max.), t
CK
=15ns
CKE≤V
IL
(max.), t
CK
=
∞
CKE≥V
IL
(min.), t
CK
=15ns,
/CS≥V
IH
(min.)
Input signals are changed
one time during 30ns
CKE≥V
IL
(min.), t
CK
=
∞
,
Input signals are stable
CKE≤V
IL
(max.), t
CK
=15ns
CKE≤V
IL
(max.), t
CK
=
∞
CKE≥V
IL
(min.), t
CK
=15ns,
/CS≥V
IH
(min.)
Input signals are changed
one time during 30ns
CKE≥V
IL
(min.), t
CK
=
∞
,
Input signals are stable
t
CCD
≥2CLKs,
I
OL
=0mA
t
RC
≥t
RC
(min.)
CKE≤0.2V
Max.
65
1
1
20
Units
mA
mA
mA
mA
Precharge Standby Current in
Power Down Mode
Precharge Standby Current in
Non-power Down Mode
I
CC2NS
I
CC3P
I
CC3PS
I
CC3N
Active Standby Current in
Power Down Mode
20
3.5
3.5
30
mA
mA
mA
mA
Active Standby Current in
Non-power Down Mode
I
CC3NS
I
CC4
I
CC5
I
CC6
Operating Current (Burst
(Note 2)
Mode)
Refresh Current
(Note 3)
30
80
155
0.475
(Note 4)
mA
mA
mA
mA
Self Refresh Current
*All voltages referenced to V
SS
.
Note 1:
I
CC1
depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during t
CK
(min.)
Note 2:
I
CC4
depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during t
CK
(min.)
Note 3:
Input signals are changed only one time during t
CK
(min.)
Note 4:
Standard power version.
Recommended DC Operating Conditions (Continued)
Symbol
I
IL
I
OL
V
OH
V
OL
Jul. 2006
5/17
Parameter
Input Leakage Current
Output Leakage Current
High Level Output Voltage
Low Level Output Voltage
Test Conditions
0≤V
I
≤V
DDQ
, V
DDQ
=V
DD
All other pins not under test=0V
0≤V
O
≤V
DDQ
, D
OUT
is disabled
I
O
=-0.1mA
I
O
=+0.1mA
Min.
-0.5
-0.5
2.4
Typ.
Max.
+0.5
+0.5
0.2
Units
uA
uA
V
V
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