EM48BM0884VTA
Revision History
Revision 0.1 (Aug. 2011)
- First release.
Aug. 2011
1/20
www.eorex.com
EM48BM0884VTA
256Mb (8M
×
4Bank
×
8) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge
• Single 3.3V
±0.3V
Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
Description
The EM48BM0884VTA is Synchronous Dynamic
Random Access Memory (SDRAM) organized
as 8Meg words x 4 banks by 8 bits. All inputs
and outputs are synchronized with the positive
edge of the clock.
The
256Mb
SDRAM
uses
synchronized
pipelined architecture to achieve high speed
data transfer rates and is designed to operate at
3.3V low power memory system. It also provides
auto refresh with power saving / down mode. All
inputs and outputs voltage levels are compatible
with LVTTL.
Available packages: TSOPII 54P 400mil.
Ordering Information
Part No
EM48BM0884VTA-6F
EM48BM0884VTA-7F
Organization
32M X 8
32M X 8
Max. Freq
166MHz @CL3
143MHz @CL3
Package
54pin TSOP(ll)
54pin TSOP(ll)
Grade
Commercial
Commercial
Pb
Free
Free
Aug. 2011
2/20
www.eorex.com
EM48BM0884VTA
Parts Naming Rules
* EOREX reserves the right to change products or specification without notice.
Aug. 2011
3/20
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EM48BM0884VTA
Pin Assignment
54pin TSOP-II
Aug. 2011
4/20
www.eorex.com
EM48BM0884VTA
Pin Description (Simplified)
Pin
38
19
Name
CLK
/CS
Function
(System Clock)
Master clock input (Active on the positive rising edge)
(Chip Select)
Selects chip when active
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
(Address)
Row address (A0 to A12) is determined by A0 to A12 level at
the bank active command cycle CLK rising edge.
CA (CA0 to CA9) is determined by A0 to A9 level at the read or
write command cycle CLK rising edge.
And this column address becomes burst access start address.
A10 defines the pre-charge mode. When A10= High at the
pre-charge command cycle, all banks are pre-charged.
But when A10= Low at the pre-charge command cycle, only the
bank that is selected by BA0/BA1 is pre-charged.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK
with /RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Write Enable)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Data Input/Output Mask)
DQM controls I/O buffers.
(Data Input/Output)
DQ pins have the same function as I/O pins on a conventional
DRAM.
(Power Supply/Ground)
V
DD
and V
SS
are power supply pins for internal circuits.
(Power Supply/Ground)
V
DDQ
and V
SSQ
are power supply pins for the output buffers.
(No Connection)
This pin is recommended to be left No Connection on the
device.
37
CKE
23~26, 22, 29~36
A0~A12
20, 21
18
BA0, BA1
/RAS
17
/CAS
16
39
2, 5, 8, 11, 44,
47, 50, 53
1,14,27/
28,41,54
3, 9, 43, 49/
6, 12, 46, 52
4, 7, 10, 13, 15,
40, 42, 45, 48, 51
/WE
DQM
DQ0~DQ7
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Aug. 2011
5/20
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