EM641FT8S Series
Low Power, 512Kx8 SRAM
Document Title
512K x8 bit Low Power Full CMOS Static RAM
Revision History
Revision No.
0.0
0.1
History
Initial Draft
0.1 Revision
I
DR
Current from 1.5uA to 7uA
t
OE
from 25nsec to 30nsec with 55ns part
Draft Date
Nov. 20, 2007
Dec. 5, 2007
Remark
Preliminary
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Emerging Memory & Logic Solutions Inc.
Zip Code : 690-719
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM641FT8S Series
Low Power, 512Kx8 SRAM
512K x8 Bit Low Power CMOS Static RAM
FEATURES
- Very high speed : 45ns
- Process Technology : 0.15um Full CMOS
- Organization : 512K x8
- Power Supply Voltage
=> EM641FT8S : 4.5V~5.5V
- Low Data Retention Voltage : 1.5V (MIN)
- Three state output and TTL Compatible
- Packaged product designed for 45/55/70ns
-
Package Type: 32L-STSOP
PRODUCT FAMILY
Product
Family
EM641FT8S-45LF
EM641FT8S-55LF
EM641FT8S-70LF
Operating
Temperature
Industrial (-40 ~ 85
o
C)
Industrial (-40 ~ 85
o
C)
Industrial (-40 ~ 85
o
C)
Power Dissipation
Vcc Range
Speed
Standby
(I
SB1
, Typ.)
1.5
µA
1.5
µA
1.5
µA
Operating
(I
CC1
.Max)
7mA
7mA
7mA
PKG Type
GENERAL DESCRIPTION
The EM641FT8S is fabricated by EMLSI’s advanced full
CMOS process technology. The families support industrial
temperature range and Chip Scale Package for user flexi-
bility of system design. The families also supports low data
retention voltage for battery back-up operation with low
data retention current.
The EM641FT8S is available in KGD, JEDEC standard 32
pin 8.0mm x 13.4mm STSOP package.
4.5V~5.5V
4.5V~5.5V
4.5V~5.5V
45ns
55ns
70ns
32-STSOP
32-STSOP
32-STSOP
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A
11
A
9
A
8
A
13
WE
A
17
A
15
V
CC
A
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EM641FT8S
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
V
SS
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
Pre-charge Circuit
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
V
CC
V
SS
Row Select
Memory Array
512K x 8
I/O
0
~ I/O
7
Data
Cont
I/O Circuit
Column Select
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
Name
CS
OE
WE
A
0
~A
18
I/O
0
~I/O
7
Function
Chip select input
Output Enable input
Write Enable input
Address Inputs
Data Inputs/Outputs
Name
V
CC
V
SS
Function
Power Supply
Ground
WE
OE
CS
Control Logic
2
EM641FT8S Series
Low Power, 512Kx8 SRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on Vcc supply relative to V
SS
Power Dissipation
Operating Temperature
Symbol
V
IN
, V
OUT
V
CC
P
D
T
A
Minimum
-0.5 to 6.0V
-0.5 to 6.0V
1.0
-40 to 85
Unit
V
V
W
o
C
Note :
Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device.
Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS
H
L
L
L
OE
X
L
X
H
WE
X
H
L
H
I/O
0-7
High-Z
Data Out
Data In
High-Z
Mode
Deselected/ Power down
Read
Write
Selected, Output Disabled
Power
Stand by
Active
Active
Active
Note :
X means don’t care. (Must be low or high state)
3
EM641FT8S Series
Low Power, 512Kx8 SRAM
RECOMMENDED DC OPERATING CONDITIONS
1)
Parameter
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
V
CC
2)
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.5
4)
Typ
-
0
-
-
Max
5.5
0
V
CC
+ 0.5
3)
0.6
Unit
V
V
V
V
Notes :
1. TA= -40 to 85
o
C, otherwise specified
2. Overshoot: VCC +1.0 V in case of pulse width < 20ns
3. Undershoot: -1.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
(f =1MHz, T
A
=25
o
C)
Item
Input capacitance
Input/Ouput capacitance
Note :
Capacitance is sampled, not 100% tested.
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC ELECTRICAL CHARACTERISTICS
(T
A
= -40
o
C to +85
o
C)
Parameter
Input leakage current
Output leakage current
Operating power supply
Symbol
I
LI
I
LO
I
CC
I
CC1
Average operating current
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
IO
=V
SS
to V
CC
I
IO
=0mA, CS=V
IL
, V
IN
=V
IH
or V
IL
Cycle time=1µs, 100% duty, I
IO
=0mA,
CS<0.2V, V
IN
<0.2V or V
IN
>V
CC
-0.2V
Cycle time = Min, I
IO
=0mA, 100% duty,
CS=V
IL
, V
IN
=V
IL
or V
IH
I
OL
= 2.1mA
I
OH
= -1.0mA
CS=V
IH
, Other inputs=V
IH
or V
IL
CS>V
CC
-0.2V
Other inputs = 0~VCC
(Typ. condition : V
CC
=5V @ 25
o
C)
(Max. condition : V
CC
=5.5V @ 85
o
C)
45ns
55ns
70ns
Test Conditions
Min
-1
-1
-
-
-
-
-
-
2.4
-
Typ
-
-
-
-
-
-
-
-
-
-
Max
1
1
5
7
65
55
45
0.4
-
1
Unit
uA
uA
mA
mA
I
CC2
V
OL
V
OH
I
SB
mA
Output low voltage
Output high voltage
Standby Current (TTL)
V
V
mA
Standby Current (CMOS)
I
SB1
LF
-
1.5
1)
20
uA
NOTES :
1.Typical values are measured at Vcc=5V, T
A
=25
o
C and not 100% tested.
4
EM641FT8S Series
Low Power, 512Kx8 SRAM
V
TM
3)
R
1
2)
Output
CL
1)
R
2
2)
AC OPERATING CONDITIONS
Test Conditions (Test
Load and Test Input/Output Reference)
Input Pulse Level : 0V to V
CC
Input Rise and Fall Time : 1V/ns
Input and Output reference Voltage : 0.5V
CC
Output Load (See right) : CL
1)
= 100pF + 1 TTL (70ns)
CL
1)
= 30pF + 1 TTL (45ns/55ns)
Notes :
1. Including scope and Jig capacitance
2. R
1
= 1800 ohm,
R
2
= 990 ohm
3. V
TM
=
V
CC
4. CL = 5pF + 1 TTL (measurement with tLZ, tOLZ, tHZ, tOHZ, tWHZ)
READ CYCLE
(V
cc
= 4.5V to 5.5V, GND = 0V, T
A
= -40
o
C to +85
o
C)
Parameter
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Symbol
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
45ns
Min
45
-
-
-
10
5
0
0
10
Max
-
45
45
25
-
-
20
15
-
Min
55
-
-
-
10
5
0
0
10
55ns
Max
-
55
55
30
-
-
20
20
-
Min
70
-
-
-
10
5
0
0
10
70ns
Max
-
70
70
35
-
-
25
25
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
(V
cc
= 4.5V to 5.5V, GND = 0V, T
A
= -40
o
C to +85
o
C)
Parameter
Write cycle time
Chip select to end of write
Address setup time
Address valid to end of write
Write pulse width
Write recovery time
Write to ouput high-Z
Data to write time overlap
Data hold from write time
End of write to output low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
45ns
Min
45
45
0
45
35
0
0
25
0
5
-
-
Max
-
-
-
-
-
-
15
Min
55
45
0
45
40
0
0
25
0
5
55ns
Max
-
-
-
-
-
-
20
Min
70
60
0
60
50
0
0
30
-
-
0
5
70ns
Max
-
-
-
-
-
-
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
-
-
ns
ns
5
FPGA/CPLD
