EM620FV8BS Series
Low Power, 256Kx8 SRAM
Document Title
256K x8 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
0.0
0.1
History
Initial Draft
0.1 Revision
Revised VOH(2.2v to 2.4v),tOH(15ns to 10ns),
tOE-55(30ns to 25ns), tWP-55(45ns to 40ns),
tWP-70(55ns to 50ns), tWHZ-70(25ns to 20ns),
ICC(2mA to 3mA), ICC1(2mA to 3mA)
V
IH
level change from 2.0V to 2.2V
Fix typo error
Draft Date
June 28, 2007
July 2, 2007
Remark
0.2
0.3
0.2 Revision
0.3 Revision
Aug. 16, 2007
Nov. 13, 2007
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Emerging Memory & Logic Solutions Inc.
Zip Code : 690-719
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM620FV8BS Series
Low Power, 256Kx8 SRAM
256K x8 Bit Low Power and Low Voltage CMOS Static RAM
FEATURES
- Process Technology : 0.15mm Full CMOS
- Organization :256K x8
- Power Supply Voltage
=> EM620FV8BS Series : 2.7V~3.6V
- Low Data Retention Voltage : 1.5V (MIN)
- Three state output and TTL Compatible
- Packaged product designed for 45/55/70ns
-
Package Type: 32-sTSOP1
PRODUCT FAMILY
Product
Family
EM620FV8BS-45LF
EM620FV8BS-55LF
EM620FV8BS-70LF
Operating
Temperature
Industrial (-40 ~ 85
o
C)
Industrial (-40 ~ 85
o
C)
Industrial (-40 ~ 85
o
C)
Power Dissipation
Vcc Range
Speed
Standby
(I
SB1
, Typ.)
1
µA
1
µA
1
µA
Operating
(I
CC1
.Max)
3mA
3mA
3mA
PKG Type
GENERAL DESCRIPTION
The EM620FV8BS series are fabricated by EMLSI’s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale Pack-
age for user flexibility of system design. The families also
supports low data retention voltage for battery back-up
operation with low data retention current.
The EM620FV8BS series are available in KGD, JEDEC
standard 32 pin 8mm x 13.4mm sTSOP package.
2.7V~3.6V
2.7V~3.6V
2.7V~3.6V
45ns
55ns
70ns
32-sTSOP
32-sTSOP
32-sTSOP
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Pre-charge Circuit
A11
A9
A8
A13
WE
CS2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EM620FV8BS-45LF
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
VSS
I/O 2
I/O 1
I/O 0
A0
A1
A2
A3
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
V
CC
V
SS
Row Select
Memory Array
1024 x 2048
I/O0 ~ I/O7
Data
Cont
I/O Circuit
Column Select
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
Name
CS1,CS2
OE
WE
A0~A17
I/O0~I/O7
Function
Chip select inputs
Output Enable input
Write Enable input
Address Inputs
Data Inputs/Outputs
Name
Vcc
Vss
NC
Function
Power Supply
Ground
No Connection
WE
OE
CS1
CS2
Control Logic
2
EM620FV8BS Series
Low Power, 256Kx8 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Operating Temperature
Symbol
V
IN
, V
OUT
V
CC
P
D
T
A
Minimum
-0.2 to 4.0V
-0.2 to 4.0V
1.0
-40 to 85
Unit
V
V
W
o
C
*
Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional oper-
ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
FUNCTIONAL DESCRIPTION
CS1
H
X
L
L
L
CS2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O
0-7
High-Z
High-Z
High-Z
Data Out
Data In
Mode
Deselected
Deselected
Output Disabled
Read
Write
Power
Stand by
Stand by
Active
Active
Active
Note: X means don’t care. (Must be low or high state)
3
EM620FV8BS Series
Low Power, 256Kx8 SRAM
RECOMMENDED DC OPERATING CONDITIONS
1)
Parameter
Supply voltage
Ground
Input high voltage
Input low voltage
1.
2.
3.
4.
Symbol
V
CC
V
SS
V
IH
V
IL
Min
2.7
0
2.2
-0.2
3)
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+ 0.2
2)
0.6
Unit
V
V
V
V
T
A
= -40 to 85
o
C, otherwise specified
Overshoot: V
CC
+2.0 V in case of pulse width < 20ns
Undershoot: -2.0 V in case of pulse width < 20ns
Overshoot and undershoot are sampled, not 100% tested
.
CAPACITANCE
1)
(f =1MHz, T
A
=25
o
C)
Item
Input capacitance
Input/Ouput capacitance
1. Capacitance is sampled, not 100% tested.
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Parameter
Input leakage current
Output leakage current
Operating power supply
Symbol
I
LI
I
LO
I
CC
I
CC1
Average operating current
I
CC2
V
OL
V
OH
I
SB
V
IN
=V
SS
to V
CC
CS1=V
IH
or CS2=V
IL
or OE=V
IH
or WE=V
IL
V
IO
=V
SS
to V
CC
I
IO
=0mA, CS1=V
IL
, CS2=WE=V
IH
, V
IN
=V
IH
or V
IL
Cycle time=1µs, 100% duty, I
IO
=0mA,
CS1<0.2V, CS2>V
CC
-0.2V,
V
IN
<0.2V or V
IN
>V
CC
-0.2V
Cycle time = Min, I
IO
=0mA, 100% duty,
CS1=V
IL
, CS2=V
IH,
V
IN
=V
IL
or V
IH
I
OL
= 2.1mA
I
OH
= -1.0mA
CS1=V
IH
, CS2=V
IL
, Other inputs=V
IH
or V
IL
CS1>V
CC
-0.2V, CS2>V
CC
-0.2V (CS1 controlled)
or 0V<CS2<0.2V (CS2 controlled),
Other inputs = 0~V
CC
(Typ. condition : V
CC
=3.3V @ 25
o
C)
(Max. condition : V
CC
=3.6V @ 85
o
C)
Test Conditions
Min
-1
-1
-
-
45ns
55ns
70ns
-
-
-
-
2.4
-
Typ
-
-
-
-
-
-
-
-
-
-
Max
1
1
3
3
35
30
25
0.4
-
0.3
Unit
uA
uA
mA
mA
mA
Output low voltage
Output high voltage
Standby Current (TTL)
V
V
mA
Standby Current (CMOS)
I
SB1
LF
-
1
1)
10
uA
NOTES
1. Typical values are measured at Vcc=3.3V, T
A
=
25
o
C and not 100% tested.
4
EM620FV8BS Series
Low Power, 256Kx8 SRAM
V
TM3)
R
12)
AC OPERATING CONDITIONS
Test Conditions (Test
Load and Test Input/Output Reference)
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL
1)
= 100pF + 1 TTL (70ns)
CL
1)
= 30pF + 1 TTL (45ns/55ns)
1. Including scope and Jig capacitance
2. R
1
=3070 ohm
,
R
2
=3150 ohm
3. V
TM
=2.8V
4. CL = 5pF + 1 TTL (measurement with t
LZ1,2
, t
HZ1,2
, t
OLZ
, t
OHZ
, t
WHZ
)
CL
1)
R
22)
READ CYCLE
(V
cc
= 2.7V to 3.6V, Gnd = 0V, T
A
= -40
o
C to +85
o
C)
Parameter
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Symbol
t
RC
t
AA
t
CO1,
t
CO2
t
OE
t
LZ1,
t
LZ2
t
OLZ
t
HZ1,
t
HZ2
t
OHZ
t
OH
45ns
Min
45
-
-
-
10
5
0
0
10
Max
-
45
45
25
-
-
20
15
-
Min
55
-
-
-
10
5
0
0
10
55ns
Max
-
55
55
25
-
-
20
20
-
Min
70
-
-
-
10
5
0
0
10
70ns
Max
-
70
70
35
-
-
25
25
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
(V
cc
= 2.7V to 3.6V, Gnd = 0V, T
A
= -40
o
C to +85
o
C)
Parameter
Write cycle time
Chip select to end of write
Address setup time
Address valid to end of write
Write pulse width
Write recovery time
Write to ouput high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
Symbol
t
WC
t
CW1,
t
CW2
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
45ns
Min
45
45
0
45
35
0
0
25
0
5
-
-
Max
-
-
-
-
-
-
15
55
45
0
45
40
0
0
25
0
5
55ns
Min
Max
-
-
-
-
-
-
20
Min
70
60
0
60
50
0
0
30
-
-
0
5
70ns
Max
-
-
-
-
-
-
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
-
-
ns
ns
5
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