EM681FV16AU Series
Low Power, 512Kx16 SRAM
Document Title
512K x16 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History2.1
Revision No.
0.0
History
Initial Draft
Production code change from
EM681FV16U-45LL to
EM681FV16U-45LF
Production code change from
EM681FV16U-45LF to
EM681FV16AU-45LF
Product code table update
Fix typo error
Draft Date
Oct. 26, 2006
Remark
Preliminary
0.1
0.1 Revision
Jan. 18, 2007
0.2
0.3
0.4
0.2 Revision
0.3 Revision
0.4 Revision
April. 10, 2007
June 15, 2007
Nov. 12, 2007
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Zip Code : 690-719
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM681FV16AU Series
Low Power, 512Kx16 SRAM
FEATURES
•
•
•
•
•
•
Process Technology : 0.15µm Full CMOS
Organization : 512K x 16 bit
Power Supply Voltage : 2.7V ~ 3.6V
Low Data Retention Voltage : 1.5V (Min.)
Three state output and TTL Compatible
Package Type : 44-TSOP2
GENERAL DESCRIPTION
The EM681FV16AU is fabricated by EMLSI’s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The fami-
lies also supports low data retention voltage for battery
back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product
Family
EM681FV16AU-45LF
EM681FV16AU-55LF
EM681FV16AU-70LF
Operating
Temperature
Industrial (-40 ~ 85
o
C)
Industrial (-40 ~ 85
o
C)
Industrial (-40 ~ 85
o
C)
Vcc Range
Speed
Standby
(I
SB1
, Typ.)
2
µA
2
µA
2
µA
Operating
(I
CC1
.Max)
4mA
4mA
4mA
PKG Type
2.7V~3.6V
2.7V~3.6V
2.7V~3.6V
45ns
55ns
70ns
44-TSOP2
44-TSOP2
44-TSOP2
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Pre-charge Circuit
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
V
CC
Row Select
V
SS
Memory Array
2048 x 4096
I/O0 ~ I/O7
I/O8 ~ I/O15
Data
Cont
Data
Cont
I/O Circuit
Column Select
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
44-TSOP2 : Top view
WE
OE
UB
LB
CS
Control Logic
Name
CS
OE
WE
A
0
~A
18
Function
Chip select inputs
Output Enable input
Write Enable input
Address Inputs
Name
Vcc
Vss
UB
LB
NC
Function
Power Supply
Ground
Upper Byte (I/O
8~15
)
Lower Byte (I/O
0~7
)
No Connected
I/O
0
~I/O
15
Data Inputs/outputs
2
EM681FV16AU Series
Low Power, 512Kx16 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Operating Temperature
Symbol
V
IN
, V
OUT
V
CC
P
D
T
A
Minimum
-0.2 to 4.0V
-0.2 to 4.0V
1.0
-40 to 85
Unit
V
V
W
o
C
*
Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional oper-
ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
FUNCTIONAL DESCRIPTION
CS
H
X
L
L
L
L
L
L
L
OE
X
X
H
L
L
L
X
X
X
WE
X
X
H
H
H
H
L
L
L
LB
X
H
X
L
H
L
L
H
L
UB
X
H
X
H
L
L
H
L
L
I/O
0-7
High-Z
High-Z
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
I/O
8-15
High-Z
High-Z
High-Z
High-Z
Data Out
Data Out
High-Z
Data In
Data In
Mode
Deselected
Deselected
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Power
Stand by
Stand by
Active
Active
Active
Active
Active
Active
Active
Note: X means don’t care. (Must be low or high state)
3
EM681FV16AU Series
Low Power, 512Kx16 SRAM
RECOMMENDED DC OPERATING CONDITIONS
1)
Parameter
Supply voltage
Ground
Input high voltage
Input low voltage
1.
2.
3.
4.
Symbol
V
CC
V
SS
V
IH
V
IL
Min
2.7
0
2.2
-0.2
3)
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+ 0.2
2)
0.6
Unit
V
V
V
V
T
A
= -40 to 85
o
C, otherwise specified
Overshoot: V
CC
+2.0 V in case of pulse width < 20ns
Undershoot: -2.0 V in case of pulse width < 20ns
Overshoot and undershoot are sampled, not 100% tested
.
CAPACITANCE
1)
(f =1MHz, T
A
=25
o
C)
Item
Input capacitance
Input/Ouput capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Parameter
Input leakage current
Output leakage current
Operating power supply
Symbol
I
LI
I
LO
I
CC
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
Standby Current (TTL)
V
OL
V
OH
I
SB
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
or LB=UB=V
IH
V
IO
=V
SS
to V
CC
I
IO
=0mA, CS=V
IL
, WE=V
IH
, V
IN
=V
IH
or V
IL
Cycle time=1µs, 100% duty, I
IO
=0mA,
CS<0.2V, LB<0.2V or/and UB<0.2V,
V
IN
<0.2V or V
IN
>V
CC
-0.2V
Cycle time = Min, I
IO
=0mA, 100% duty,
CS=V
IL
, LB=V
IL
or/and UB=V
IL ,
V
IN
=V
IL
or V
IH
I
OL
= 2.1mA
I
OH
= -1.0mA
CS=V
IH
, Other inputs=V
IH
or V
IL
CS>V
CC
-0.2V
Test Conditions
Min
-1
-1
-
-
45ns
55ns
70ns
Typ
-
-
-
-
Max
1
1
2
4
45
35
25
0.4
-
0.5
Unit
uA
uA
mA
mA
-
-
2.2
-
-
-
-
-
mA
V
V
mA
Standby Current (CMOS)
I
SB1
Other inputs=0 ~ V
CC
(Typ. condition : V
CC
=3.3V @ 25
o
C)
(Max. condition : V
CC
=3.6V @ 85
o
C)
LF
-
2
15
uA
4
EM681FV16AU Series
Low Power, 512Kx16 SRAM
AC OPERATING CONDITIONS
Test Conditions (Test
Load and Test Input/Output Reference)
Input Pulse Level : 0.4 to 2.4V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL
1)
= 100pF + 1 TTL (70nsec)
CL
1)
= 30pF + 1 TTL (45ns/55ns)
1. Including scope and Jig capacitance
2. R
1
=3070 ohm
,
R
2
=3150 ohm
3. V
TM
=2.8V
4. CL = 5pF + 1 TTL (measurement with t
LZ
, t
HZ
, t
OLZ
, t
OHZ
, t
WHZ
)
R
12)
V
TM3)
CL
1)
R
22)
READ CYCLE
(V
cc
=2.7 to 3.6V, Gnd = 0V, T
A
= -40
o
C to +85
o
C)
Parameter
Read cycle time
Address access time
Chip select to output
Output enable to valid output
UB, LB access time
Chip select to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to how-Z output
Output disable to high-Z output
Output hold from address change
Symbol
t
RC
t
AA
t
co
t
OE
t
BA
t
LZ
t
BLZ
t
OLZ
t
HZ
t
BHZ
t
OHZ
t
OH
45ns
Min
45
-
-
-
Max
-
45
45
30
45
5
5
5
0
0
0
10
-
-
-
20
20
20
-
5
5
5
0
0
0
10
Min
55
-
-
-
55ns
Max
-
55
55
35
55
-
-
-
20
20
20
-
5
5
5
0
0
0
10
Min
70
-
-
-
70ns
Max
-
70
70
35
70
-
-
-
25
25
25
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
(V
cc
=2.7 to 3.6V, Gnd = 0V, T
A
= -40
o
C to +85
o
C)
Parameter
Write cycle time
Chip select to end of write
Address setup time
Address valid to end of write
UB, LB valid to end of write
Write pulse width
Write recovery time
Write to ouput high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
Symbol
t
WC
t
CW
t
As
t
AW
t
BW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
45ns
Min
45
45
0
45
45
45
0
0
25
0
5
-
-
Max
-
-
-
-
-
-
-
20
Min
55
45
0
45
45
45
0
0
30
0
5
55ns
Max
-
-
-
-
-
-
-
20
Min
70
60
0
60
60
55
0
0
30
-
0
5
70ns
Max
-
-
-
-
-
-
-
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
ns
ns
5
嵌入式系统
