EN25B80
EN25B80
8 Mbit Serial Flash Memory with Boot and Parameter Sectors
FEATURES
•
Single power supply operation
- Full voltage range: 2.7-3.6 volt
•
8 M-bit Serial Flash
- 8 M-bit/1024 K-byte/4096 pages
- 256 bytes per programmable page
•
High performance
- 75MHz clock rate
•
Low power consumption
- 5 mA typical active current
- 1
μA
typical power down current
•
Flexible Sector Architecture:
- Two 4-Kbyte, one 8-Kbyte, one 16-Kbyte,one
32-Kbyte, and fifteen 64-Kbyte sectors
•
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
•
-
-
-
-
High performance program/erase speed
Byte program time: 7µs typical
Page program time: 1.5ms typical
Sector erase time: 300 to 800ms typical
Chip erase time: 10 Seconds typical
•
Minimum 100K endurance cycle
•
Package Options
- 8 pins SOP 200mil body width
- 8 contact VDFN
- 8 pins PDIP
- All Pb-free packages are RoHS compliant
•
Commercial and industrial temperature
Range
GENERAL DESCRIPTION
The EN25B80 is a 8M-bit (1024K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25B80 has twenty sectors including fifteen sectors of 64KB, one sector of 32KB, one sector of
16KB, one sector of 8KB and two sectors of 4KB. This device is designed to allow either single Sector at a
time or full chip erase operation. The EN25B80 can protect boot code stored in the small sectors for either
bottom or top boot configurations. The device can sustain a minimum of 100K program/erase cycles on
each sector.
This Data Sheet may be revised by subsequent versions
1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2006/12/25
EN25B80
Figure.1 CONNECTION DIAGRAMS
8 - LEAD SOP
8 - CONTACT VDFN
Figure 2. BLOCK DIAGRAM
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2006/12/25
EN25B80
SIGNAL DESCRIPTION
Serial Data Input (DI)
The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be
serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK)
input pin.
Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from (shifted
out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices
power consumption will be at standby levels unless an internal erase, program or status register cycle is
in progress. When CS# is brought low the device will be selected, power consumption will increase to
active levels and instructions can be written to and data read from the device. After power-up, CS# must
transition from high to low before a new instruction will be accepted.
Hold (HOLD#)
The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought low,
while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
(don’t care). The hold function can be useful when multiple devices are sharing the same SPI signals.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status Register Protect
(SRP) bits, a portion or the entire memory array can be hardware protected.
Table 1. PIN Names
Symbol
CLK
DI
DO
CS#
WP#
HOLD#
Vcc
Vss
Pin Name
Serial Clock Input
Serial Data Input
Serial Data Output
Chip Enable
Write Protect
Hold Input
Supply Voltage (2.7-3.6V)
Ground
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2006/12/25
EN25B80
MEMORY ORGANIZATION
The memory is organized as:
1,048,576 bytes
Flexible Sector Architecture
Two 4-Kbyte, one 8-Kbyte, one 16-Kbyte,one 32-Kbyte, and fifteen 64-Kbyte sectors
Bottom or top boot configurations
4096 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or
Bulk Erasable but not Page Erasable.
Table 2a.
Bottom Boot Block Sector Architecture
Sector
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SECTOR SIZE (KByte)
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
32
16
8
4
4
Address range
F0000h – FFFFFh
E0000h – EFFFFh
D0000h – DFFFFh
C0000h – CFFFFh
B0000h – BFFFFh
A0000h – AFFFFh
90000h – 9FFFFh
80000h – 8FFFFh
70000h – 7FFFFh
60000h – 6FFFFh
50000h – 5FFFFh
40000h – 4FFFFh
30000h – 3FFFFh
20000h – 2FFFFh
10000h – 1FFFFh
08000h – 0FFFFh
04000h – 07FFFh
02000h – 03FFFh
01000h – 01FFFh
00000h – 00FFFh
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2006/12/25
EN25B80
Table 2b.
Top Boot Block Sector Architecture (Special order)
Sector
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SECTOR SIZE (KByte)
4
4
8
16
32
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
Address range
FF000h – FFFFFh
FE000h – FEFFFh
FC000h – FDFFFh
F8000h – FBFFFh
F0000h – F7FFFh
E0000h – EFFFFh
D0000h – DFFFFh
C0000h – CFFFFh
B0000h – BFFFFh
A0000h – AFFFFh
90000h – 9FFFFh
80000h – 8FFFFh
70000h – 7FFFFh
60000h – 6FFFFh
50000h – 5FFFFh
40000h – 4FFFFh
30000h – 3FFFFh
20000h – 2FFFFh
10000h – 1FFFFh
00000h – 0FFFFh
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2006/12/25
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