Enpirion
®
Power Datasheet
EN5367QI 6A PowerSoC
Highly Integrated Synchronous Buck
With Integrated Inductor
Description
The EN5367QI is a Power System on a Chip
(PowerSoC) DC to DC converter with an integrated
inductor,
PWM
controller,
MOSFETs
and
compensation to provide the smallest solution size in
a 5.5x10x3mm 54-pin QFN module. It offers high
efficiency, excellent line and load regulation over
temperature and up to the full 6A load range. The
EN5367QI is specifically designed to meet the
precise voltage and fast transient requirements of
high-performance, low-power processor, DSP, FPGA,
memory boards and system level applications in
distributed power architecture. The EN5367QI also
features switching frequency synchronization with an
external clock, programmable soft-start as well as
thermal shutdown, over-current and short circuit
protection. The device’s advanced circuit techniques,
ultra high switching frequency, and proprietary
integrated inductor technology deliver high-quality,
ultra compact, non-isolated DC-DC conversion.
The Altera Enpirion integrated inductor solution
significantly helps to reduce noise. The complete
power converter solution enhances productivity by
offering greatly simplified board design, layout and
manufacturing requirements. All Altera Enpirion
products are RoHS compliant and lead-free
manufacturing environment compatible.
Features
•
•
•
•
•
•
•
•
•
High Efficiency (Up to 93%)
Excellent Ripple and EMI Performance
Up to 6A Continuous Operating Current
Input Voltage Range (2.5V to 5.5V)
Frequency Synchronization (External Clock)
3% V
OUT
Accuracy (Over Line/Load/Temperature)
Optimized Total Solution Size (160mm
2
)
Programmable Soft-Start
Output Enable Pin and Power OK
•
Thermal Shutdown, Over-Current, Short Circuit,
and Under-Voltage Lockout Protection (UVLO)
•
RoHS Compliant, MSL Level 3, 260°C Reflow
Applications
•
Point of Load Regulation for Low-Power, ASICs
Multi-Core and Communication Processors, DSPs,
FPGAs and Distributed Power Architectures
•
Blade Servers, RAID Storage and LAN/SAN
Adapter Cards, Wireless Base Stations, Industrial
Automation, Test and Measurement, Embedded
Computing, and Printers
•
Beat Frequency/Noise Sensitive Applications
0.1µF
0.1µF
Efficiency vs. Output Current
100
V
IN
10Ω
47µF
1206
BTMP PG VDDB BGND
PVIN
VOUT
V
OUT
EFFICIENCY (%)
47µF
1206
R
A
C
A
90
80
70
60
50
40
30
20
10
0
0
1
2
3
4
OUTPUT CURRENT (A)
5
6
CONDITIONS
V
IN
= 5.0V
VOUT = 3.3V
VOUT = 1.2V
EN5367QI
AVIN
ENABLE
VFB
47nF
0805
Actual Solution Size
160mm
2
0.1µF
SS
R
CA
PGND
47nF
PGND
AGND
SYNC
R
B
Figure 1.
Simplified Applications Circuit
Figure 2.
Highest Efficiency in Smallest Solution Size
www.altera.com/enpirion
07013
October 11, 2013
Rev D
EN5367QI
Ordering Information
Part Number
Package Markings
Temp Rating (°C)
Package Description
EN5367QI
EN5367QI
-40 to +85
54-pin (5.5mm x 10mm x 3mm) QFN T&R
EN5367QI
QFN Evaluation Board
EVB-EN5367QI
Packing and Marking Information:
www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Pin Assignments (Top View)
NC(SW)
AGND
AVIN
ENABLE
38
NC(SW)
NC(SW)
NC(SW)
EAOUT
NC
POK
VFB
NC
NC
NC
NC
49
46
44
48
43
NC
53
52
50
47
54
42
40
39
51
45
NC
NC
NC
NC
NC
NC
NC
NC
NC
41
37
NC
SS
1
2
3
4
5
6
7
8
9
21
17
KEEP OUT
36
35
34
SYNC
BGND
VDDB
BTMP
PG
PVIN
PVIN
PVIN
PVIN
55
PGND
KEEP OUT
25
26
33
32
31
30
29
28
KEEP OUT
23
13
16
19
15
11
12
14
18
20
22
24
10
VOUT
VOUT
VOUT
VOUT
VOUT
PGND
PGND
NC(SW)
NC(SW)
PGND
PGND
PGND
Figure 3:
Pin Out Diagram (Top View)
NOTE A:
NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B:
Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to the PCB. Refer to Figure 9 for details.
NOTE C:
White ‘dot’ on top left is pin 1 indicator on top of the device package.
Pin Description
PIN
1-9, 18,
37, 40,
42, 45,
48, 53-54
10-17
19-20,
49-52
21-27
28-31
32
NAME
NC
VOUT
NC(SW)
PGND
PVIN
PG
FUNCTION
NO CONNECT – These pins may be internally connected. Do not connect them to each other
or to any other electrical signal. Failure to follow this guideline may result in device damage.
Regulated converter output. Connect these pins to the load and place output capacitor
between these pins and PGND pins 21-24.
NO CONNECT – These pins are internally connected to the common switching node of the
internal MOSFETs. They are not to be electrically connected to any external signal, ground, or
voltage. Failure to follow this guideline may result in damage to the device.
Input/Output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT and PVIN pin descriptions for more details.
Input power supply. Connect to input power supply. Decouple with input capacitor to PGND
pins 25-27.
High-side FET gate. This pin needs to be connected to BTMP using a 0.1µF capacitor.
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07013
October 11, 2013
PGND
PGND
VOUT
VOUT
VOUT
NC
27
www.altera.com/enpirion
Rev D
EN5367QI
PIN
33
34
35
36
38
39
41
43
44
46
47
55
NAME
BTMP
VDDB
BGND
SYNC
ENABLE
POK
EAOUT
SS
VFB
AGND
AVIN
PGND
FUNCTION
Low side of the flying capacitor that drives the high-side FET gate. Connect to PG using a
0.1µF capacitor.
Regulated voltage used for internal control circuitry. Decouple with a 0.1µF capacitor to
BGND.
Internal GND for VDDB. Connect to VDDB using a 0.1µF capacitor. Do not tie to any grounds
on the PCB.
A clocked input to this pin will synchronize the internal switching frequency to the external
signal. If the SYNC function is not to be used, this pin has to be grounded. Do not float this pin
or tie it to a static high voltage.
Input Enable. Applying a logic high enables the output and initiates a soft-start. Applying a
logic low disables the output.
Power OK is an open drain transistor used for power system state indication. POK is logic
high when VOUT is within -10% of VOUT nominal.
Optional Error Amplifier output. Allows for customization of the control loop.
Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The value
of this capacitor determines the startup time.
External Feedback Input. The feedback loop is closed through this pin. A voltage divider at
VOUT is used to set the output voltage. The midpoint of the divider is connected to VFB. A
phase lead capacitor from this pin to VOUT is also required to stabilize the loop.
Analog Ground. This is the Ground return for the controller. Needs to be connected to the
GND plane using a via right next to the pin.
Input power supply for the controller. Needs to be decoupled to AGND with a 0.1µF capacitor
and connected to the input voltage at a quiet point through a 10Ω resistor.
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat
sinking purposes through a matrix of vias.
3
07013
October 11, 2013
www.altera.com/enpirion
Rev D
EN5367QI
Absolute Maximum Ratings
CAUTION:
Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
PARAMETER
Voltages on : PVIN, AVIN, VOUT
Voltages on: ENABLE, POK, SYNC
Voltages on: VFB, SS
Storage Temperature Range
Maximum Operating Junction Temperature
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
ESD Rating (based on Human Body Model)
ESD Rating (based on CDM)
SYMBOL
MIN
-0.3
-0.3
-0.3
MAX
6.5
V
IN
+0.3
2.75
150
150
260
2000
500
UNITS
V
V
V
°C
°C
°C
V
V
T
STG
T
J-ABS Max
-65
Recommended Operating Conditions
PARAMETER
Input Voltage Range
Output Voltage Range (Note 1)
Output Current
Operating Ambient Temperature
Operating Junction Temperature
SYMBOL
V
IN
V
OUT
I
OUT
T
A
T
J
MIN
2.5
0.60
-40
-40
MAX
5.5
V
IN
– V
DO
6
+85
+125
UNITS
V
V
A
°C
°C
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient (0 LFM) (Note 2)
Thermal Resistance: Junction to Case (0 LFM)
Thermal Shutdown
Thermal Shutdown Hysteresis
SYMBOL
θ
JA
θ
JC
T
SD
T
SDH
TYP
22
2
150
20
UNITS
°C/W
°C/W
°C
°C
Note 1:
V
DO
(Dropout Voltage) is defined as (I
LOAD
x Dropout Resistance). Please refer to Electrical Characteristics Table.
Note 2:
Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for
high thermal conductivity boards.
4
07013
October 11, 2013
www.altera.com/enpirion
Rev D
EN5367QI
Electrical Characteristics
NOTE: V
IN
=5.5V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.
Typical values are at T
A
= 25°C.
PARAMETER
Operating Input
Voltage
SYMBOL
V
IN
TEST CONDITIONS
MIN
2.5
TYP
MAX
5.5
UNITS
V
V
V
µA
Under Voltage Lock-
V
UVLOR
out – V
IN
Rising
Under Voltage Lock-
V
UVLOF
out – V
IN
Falling
Shut-Down Supply
Current
Feedback Pin
Voltage
Feedback Pin
Voltage
Feedback pin Input
Leakage Current
(Note 3)
V
OUT
Rise Time
(Note 3)
Soft Start Capacitor
Range
Output Drop Out
Voltage Resistance
(Note 3)
Continuous Output
Current
Over Current Trip
Level
Disable Threshold
ENABLE Threshold
ENABLE Lockout
Time
ENABLE pin Input
Current
Switching
Frequency (Free
Running)
External SYNC
Clock Frequency
Lock Range
SYNC Pin
Threshold – Lo
SYNC Pin
Threshold – Hi
I
S
V
FB
V
FB
Voltage above which UVLO is not
asserted
Voltage below which UVLO is
asserted
ENABLE=0V
Feedback node voltage at:
V
IN
= 5V, ILOAD = 0, T
A
= 25°C
Feedback node voltage at:
2.5V ≤ V
IN
≤ 5.5V
0A ≤ ILOAD ≤ 6A
VFB pin input leakage current
Measured from when V
IN
> V
UVLOR
&
ENABLE pin voltage crosses its logic
high threshold to when V
OUT
reaches
its final value. C
SS
= 47 nF
0.735
0.7275
2.25
2.05
100
0.75
0.75
0.765
0.7725
V
V
I
FB
-5
5
nA
t
RISE
2.82
3.76
4.70
ms
C
SS_RANGE
V
DO
R
DO
I
OUT_Max_Cont
I
OCP
V
DISABLE
V
ENABLE
T
ENLOCKOUT
I
ENABLE
F
SW
ENABLE pin has ~180kΩ pull down
Free Running frequency of oscillator
V
IN
= 5V, V
OUT
= 1.2V
ENABLE pin logic low.
ENABLE pin logic high
2.5V ≤ V
IN
≤ 5.5V
V
INMIN
- V
OUT
at Full load
Input to Output Resistance
10
300
50
0
9
0.0
1.8
2.4
30
4
68
600
100
6
nF
mV
mΩ
A
A
0.6
V
IN
V
V
ms
µA
MHz
F
PLL_LOCK
V
SYNC_LO
V
SYNC_HI
Range of SYNC clock frequency
SYNC Clock Logic Level
SYNC Clock Logic Level (Note 4)
3.2
4.2
0.8
MHz
V
V
1.8
2.5
5
07013
October 11, 2013
www.altera.com/enpirion
Rev D
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