Stratix
®
Programmable Logic
Device Family
Data Sheet
April 2002, ver. 2.0
Introduction
Preliminary
Information
The Stratix family of programmable logic devices (PLDs) is based on a
1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to
114,140 logic elements (LEs) and up to 10 Mbits of RAM. Stratix devices
offer up to 28 digital signal processing (DSP) blocks with up to
224 (9-bit
×
9-bit) embedded multipliers, optimized for DSP applications
that enable efficient implementation of high-performance filters and
multipliers. Stratix devices support various I/O standards and also offer
a complete clock management solution with its hierarchical clock
structure with up to 420-MHz performance and up to 12 phase-locked
loops (PLLs).
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Altera Corporation
DS-STXFAMLY-2.0
10,570 to 114,140 LEs; see
Table 1
Up to 10,118,016 RAM bits (1,264,752 bytes) available without
reducing logic resources
TriMatrix
TM
memory consisting of three RAM block sizes to
implement true dual-port memory and first-in first-out (FIFO)
buffers up to 312 MHz
High-speed DSP blocks provide dedicated implementation of
multipliers (at up to 250 MHz), multiply- accumulate functions, and
finite impulse response (FIR) filters
Up to 16 global clocks with 22 clocking resources per device region
Up to 12 enhanced PLLs per device provide spread spectrum,
programmable bandwidth, clock switch-over, real-time PLL
reconfiguration, and advanced multiplication and phase shifting
Support for numerous single-ended and differential I/O standards
High-speed differential I/O support on up to 116 channels with up to
80 channels optimized for 840 megabits per second (Mbps)
Support for high-speed networking and communications bus
standards including RapidIO, UTOPIA IV, CSIX, HyperTransport
TM
technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and
SFI-4
Terminator
TM
technology provides on-chip termination for
differential and single-ended I/O pins with impedance matching
Support for high-speed external memory, including zero bus
turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM,
double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM), and
single data rate (SDR) SDRAM
Support for multiple intellectual property megafunctions from Altera
MegaCore
®
functions and Altera Megafunction Partners Program
(AMPP
SM
) megafunctions
Support for remote configuration updates
1
Stratix Programmable Logic Device Family Data Sheet
Preliminary Information
Table 1. Stratix Device Features (Part 1 of 2)
Feature
LEs
M512 RAM blocks
(32
×
18 bits)
M4K RAM blocks
(128
×
36 bits)
MegaRAM blocks
(4K
×
144 bits)
Total RAM bits
DSP blocks
Embedded multipliers
(1)
PLLs
Maximum user I/O pins
EP1S10
10,570
94
60
1
920,448
6
48
6
422
EP1S20
18,460
194
82
2
1,669,248
10
80
6
582
EP1S25
25,660
224
138
2
1,944,576
10
80
6
702
EP1S30
32,470
295
171
4
3,317,184
12
96
10
726
Stratix Device Features (Part 2 of 2)
Feature
LEs
M512 RAM blocks
(32
×
18 bits)
M4K RAM blocks
(128
×
36 bits)
MegaRAM blocks
(4K
×
144 bits)
Total RAM bits
DSP blocks
Embedded multipliers
(1)
PLLs
Maximum user I/O pins
Note to
Table 1:
(1)
EP1S40
41,250
384
183
4
3,423,744
14
112
12
818
EP1S60
57,120
574
292
6
5,215,104
18
144
12
1,018
EP1S80
79,040
767
364
9
7,427,520
22
176
12
1,234
EP1S120
114,140
1,118
520
12
10,118,016
28
224
12
1,310
This parameter lists the total number of 9
×
9-bit multipliers for each device. For the total number of 18
×
18-bit
multipliers per device, divide the total number of 9
×
9-bit multipliers by 2. For the total number of 36
×
36-bit
multipliers per device, decide the total number of 9
×
9-bit multipliers by 8.
2
Altera Corporation
Preliminary Information
Stratix Programmable Logic Device Family Data Sheet
Stratix devices are available in space-saving FineLine BGA
TM
and ball-grid
array (BGA) packages (see
Tables 2
through
4)
Table 2. Stratix Package Options & I/O Pin Counts
Device
672-Pin
BGA
341
422
469
679
679
679
679
956-Pin
BGA
672-Pin
FineLine
BGA
341
422
469
780-Pin
FineLine
BGA
422
582
593
593
1,020-Pin
FineLine
BGA
1,508-Pin
FineLine
BGA
1,923-Pin
FineLine
BGA
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
EP1S120
702
726
769
769
818
1,018
1,199
1,234
1,310
Table 3. Stratix BGA Package Sizes
Dimension
Pitch (mm)
Area (mm
2
)
Length
×
width (mm
×
mm)
672 Pin
1.27
1,225
35
×
35
956 Pin
1.27
1,600
40
×
40
Table 4. Stratix FineLine BGA Package Sizes
Dimension
Pitch (mm)
Area (mm )
Length
×
width
(mm
×
mm)
2
672 Pin
1.00
729
27
×
27
780 Pin
1.00
841
29
×
29
1,020 Pin
1.00
1,089
33
×
33
1,508 Pin
1.00
1,600
40
×
40
1,923 Pin
1.00
2,025
45
×
45
Altera Corporation
3
Stratix Programmable Logic Device Family Data Sheet
Preliminary Information
Table of
Contents
Introduction ........................................................................................................1
Features ...............................................................................................................1
Table of Contents ...............................................................................................4
Functional Description ......................................................................................5
Logic Array Blocks.............................................................................................7
Logic Elements .................................................................................................10
MultiTrack Interconnect .................................................................................18
TriMatrix Memory ...........................................................................................26
Digital Signal Processing Block......................................................................54
PLLs & Clock Networks..................................................................................76
I/O Structure ..................................................................................................105
High-Speed Differential I/O Support.........................................................128
Power Sequencing & Hot Socketing ...........................................................133
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support.....................................133
SignalTap Embedded Logic Analyzer ........................................................138
Configuration .................................................................................................138
Temperature Sensing Diode.........................................................................144
Operating Conditions....................................................................................146
Power Consumption......................................................................................157
Timing Model .................................................................................................158
Software...........................................................................................................195
Device Pin-Outs..............................................................................................195
Ordering Information....................................................................................195
4
Altera Corporation
Preliminary Information
Stratix Programmable Logic Device Family Data Sheet
Functional
Description
Stratix devices contain a two-dimensional row- and column-based
architecture to implement custom logic. A series of column and row
interconnects of varying length and speed provides signal interconnects
between logic array blocks (LABs), memory block structures, and DSP
blocks.
The logic array consists of LABs, with 10 logic elements (LEs) in each LAB.
An LE is a small unit of logic providing efficient implementation of user
logic functions. LABs are grouped into rows and columns across the
device.
M512 RAM blocks are simple dual-port memory blocks with 512 bits plus
parity (576 bits). These blocks provide dedicated simple dual-port or
single-port memory up to 18-bits wide at up to 312 MHz. M512 blocks are
grouped into columns across the device in between certain LABs.
M4K RAM blocks are true dual-port memory blocks with 4K bits plus
parity (4,608 bits). These blocks provide dedicated true dual-port, simple
dual-port, or single-port memory up to 36-bits wide at up to 312 MHz.
These blocks are grouped into columns across the device in between
certain LABs.
MegaRAM blocks are true dual-port memory blocks with 512K bits plus
parity (589,824 bits). These blocks provide dedicated true dual-port,
simple dual-port, or single-port memory up to 144-bits wide at up to
300 MHz. Several MegaRAM blocks are located individually or in pairs
within the device’s logic array.
Digital signal processing (DSP) blocks can implement up to either eight
full-precision 9
×
9-bit multipliers, four full-precision 18
×
18-bit
multipliers, or one full-precision 36
×
36-bit multiplier with add or
subtract features. These blocks also contain 18-bit input shift registers for
digital signal processing applications, including FIR and infinite impulse
response (IIR) filters. DSP blocks are grouped into two columns in each
device.
Each Stratix device I/O pin is fed by an I/O element (IOE) located at the
end of LAB rows and columns around the periphery of the device. I/O
pins support numerous single-ended and differential I/O standards. Each
IOE contains a bidirectional I/O buffer and six registers for registering
input, output, and output-enable signals. When used with dedicated
clocks, these registers provide exceptional performance and interface
support with external memory devices such as DDR SDRAM, FCRAM,
ZBT, and QDR SRAM devices.
Altera Corporation
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