Cyclone II Device Handbook, Volume 1
101 Innovation Drive
San Jose, CA 95134
www.altera.com
CII5V1-3.2
Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
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performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-
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formation and before placing orders for products or services
.
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Contents
Chapter Revision Dates ........................................................................... xi
About This Handbook ............................................................................ xiii
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiii
Section I. Cyclone II Device Family Data Sheet
Revision History .................................................................................................................................... 1–1
Chapter 1. Introduction
Introduction ............................................................................................................................................
Low-Cost Embedded Processing Solutions ..................................................................................
Low-Cost DSP Solutions .................................................................................................................
Features ...................................................................................................................................................
Document Revision History .................................................................................................................
1–1
1–1
1–1
1–2
1–8
Chapter 2. Cyclone II Architecture
Functional Description .......................................................................................................................... 2–1
Logic Elements ....................................................................................................................................... 2–2
LE Operating Modes ........................................................................................................................ 2–4
Logic Array Blocks ................................................................................................................................ 2–7
LAB Interconnects ............................................................................................................................ 2–8
LAB Control Signals ......................................................................................................................... 2–8
MultiTrack Interconnect ..................................................................................................................... 2–10
Row Interconnects .......................................................................................................................... 2–10
Column Interconnects .................................................................................................................... 2–12
Device Routing ............................................................................................................................... 2–15
Global Clock Network & Phase-Locked Loops ............................................................................... 2–16
Dedicated Clock Pins ..................................................................................................................... 2–20
Dual-Purpose Clock Pins .............................................................................................................. 2–20
Global Clock Network ................................................................................................................... 2–21
Global Clock Network Distribution ............................................................................................ 2–23
PLLs .................................................................................................................................................. 2–25
Embedded Memory ............................................................................................................................. 2–27
Memory Modes ............................................................................................................................... 2–30
Clock Modes .................................................................................................................................... 2–31
M4K Routing Interface .................................................................................................................. 2–31
Embedded Multipliers ........................................................................................................................ 2–32
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Contents
Multiplier Modes ............................................................................................................................
Embedded Multiplier Routing Interface .....................................................................................
I/O Structure & Features ....................................................................................................................
External Memory Interfacing .......................................................................................................
Programmable Drive Strength .....................................................................................................
Open-Drain Output ........................................................................................................................
Slew Rate Control ...........................................................................................................................
Bus Hold ..........................................................................................................................................
Programmable Pull-Up Resistor ..................................................................................................
Advanced I/O Standard Support ................................................................................................
High-Speed Differential Interfaces ..............................................................................................
Series On-Chip Termination .........................................................................................................
I/O Banks ........................................................................................................................................
MultiVolt I/O Interface .................................................................................................................
2–35
2–36
2–37
2–44
2–49
2–50
2–51
2–51
2–51
2–52
2–53
2–55
2–57
2–60
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 (JTAG) Boundary Scan Support .............................................................................
Configuration .........................................................................................................................................
Operating Modes ...................................................................................................................................
Configuration Schemes .........................................................................................................................
Cyclone II Automated Single Event Upset Detection ......................................................................
Custom-Built Circuitry ....................................................................................................................
Software Interface .............................................................................................................................
Document Revision History .................................................................................................................
3–1
3–5
3–5
3–6
3–7
3–7
3–7
3–8
Chapter 4. Hot Socketing & Power-On Reset
Introduction ............................................................................................................................................
Cyclone II Hot-Socketing Specifications ............................................................................................
Devices Can Be Driven before Power-Up .....................................................................................
I/O Pins Remain Tri-Stated during Power-Up ............................................................................
Hot-Socketing Feature Implementation in Cyclone II Devices .......................................................
Power-On Reset Circuitry ....................................................................................................................
"Wake-up" Time for Cyclone II Devices .......................................................................................
Conclusion ..............................................................................................................................................
Document Revision History .................................................................................................................
4–1
4–1
4–2
4–2
4–3
4–5
4–5
4–7
4–7
Chapter 5. DC Characteristics & Timing Specifications
Operating Conditions ........................................................................................................................... 5–1
Single-Ended I/O Standards .......................................................................................................... 5–5
Differential I/O Standards .............................................................................................................. 5–7
DC Characteristics for Different Pin Types ..................................................................................... 5–11
On-Chip Termination Specifications ........................................................................................... 5–12
Power Consumption ........................................................................................................................... 5–13
Timing Specifications .......................................................................................................................... 5–14
Preliminary & Final Timing Specifications ................................................................................. 5–14
Performance .................................................................................................................................... 5–15
Internal Timing ............................................................................................................................... 5–18
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Cyclone II Device Handbook, Volume 1
Altera Corporation
Contents
Cyclone II Clock Timing Parameters ...........................................................................................
Clock Network Skew Adders .......................................................................................................
IOE Programmable Delay .............................................................................................................
Default Capacitive Loading of Different I/O Standards ..........................................................
I/O Delays .......................................................................................................................................
Maximum Input & Output Clock Rate .......................................................................................
High Speed I/O Timing Specifications .......................................................................................
External Memory Interface Specifications ..................................................................................
JTAG Timing Specifications ..........................................................................................................
PLL Timing Specifications ............................................................................................................
Duty Cycle Distortion .........................................................................................................................
DCD Measurement Techniques ...................................................................................................
Document Revision History ...............................................................................................................
5–22
5–28
5–29
5–30
5–31
5–43
5–52
5–60
5–61
5–63
5–64
5–65
5–71
Chapter 6. Reference & Ordering Information
Software ..................................................................................................................................................
Device Pin-Outs .....................................................................................................................................
Ordering Information ...........................................................................................................................
Document Revision History .................................................................................................................
6–1
6–1
6–1
6–2
Section II. Clock Management
Revision History .................................................................................................................................... 6–1
Chapter 7. PLLs in Cyclone II Devices
Introduction ............................................................................................................................................ 7–1
Cyclone II PLL Hardware Overview .................................................................................................. 7–2
PLL Reference Clock Generation ................................................................................................... 7–6
Clock Feedback Modes ....................................................................................................................... 7–10
Normal Mode .................................................................................................................................. 7–10
Zero Delay Buffer Mode ................................................................................................................ 7–11
No Compensation Mode ............................................................................................................... 7–12
Source-Synchronous Mode ........................................................................................................... 7–13
Hardware Features .............................................................................................................................. 7–14
Clock Multiplication & Division .................................................................................................. 7–14
Programmable Duty Cycle ........................................................................................................... 7–15
Phase-Shifting Implementation .................................................................................................... 7–16
Control Signals ................................................................................................................................ 7–17
Manual Clock Switchover ............................................................................................................. 7–20
Clocking ................................................................................................................................................ 7–21
Global Clock Network ................................................................................................................... 7–21
Clock Control Block ....................................................................................................................... 7–24
Global Clock Network Clock Source Generation ...................................................................... 7–26
Global Clock Network Power Down ........................................................................................... 7–28
clkena signals .................................................................................................................................. 7–29
Board Layout ........................................................................................................................................ 7–30
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Cyclone II Device Handbook, Volume 1
