EP4CGX30CF23C7,EP4CGX30CF23C7 pdf中文资料,EP4CGX30CF23C7引脚图,EP4CGX30CF23C7电路-Datasheet-电子工程世界

文档预览

1. Cyclone IV FPGA Device Family

Overview

March 2016

CYIV-51001-2.0

Altera’s new Cyclone

IV FPGA device family extends the Cyclone FPGA series

leadership in providing the market’s lowest-cost, lowest-power FPGAs, now with a

transceiver variant. Cyclone IV devices are targeted to high-volume, cost-sensitive

applications, enabling system designers to meet increasing bandwidth requirements

while lowering costs.

Built on an optimized low-power process, the Cyclone IV device family offers the

following two variants:

■

Cyclone IV E—lowest power, high functionality with the lowest cost

Cyclone IV GX—lowest power and lowest cost FPGAs with 3.125 Gbps

transceivers

Cyclone IV E devices are offered in core voltage of 1.0 V and 1.2 V.

For more information, refer to the

Power Requirements for Cyclone IV Devices

chapter.

Providing power and cost savings without sacrificing performance, along with a

low-cost integrated transceiver option, Cyclone IV devices are ideal for low-cost,

small-form-factor applications in the wireless, wireline, broadcast, industrial,

consumer, and communications industries.

Cyclone IV Device Family Features

The Cyclone IV device family offers the following features:

■

Low-cost, low-power FPGA fabric:

■

6K to 150K logic elements

Up to 6.3 Mb of embedded memory

Up to 360 18 × 18 multipliers for DSP processing intensive applications

Protocol bridging applications for under 1.5 W total power

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html.

Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

Cyclone IV Device Handbook,

Volume 1

March 2016

Feedback Subscribe

1–2

Chapter 1: Cyclone IV FPGA Device Family Overview

Cyclone IV Device Family Features

■

Cyclone IV GX devices offer up to eight high-speed transceivers that provide:

■

Data rates up to 3.125 Gbps

8B/10B encoder/decoder

8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer

(PCS) interface

Byte serializer/deserializer (SERDES)

Word aligner

Rate matching FIFO

TX bit slipper for Common Public Radio Interface (CPRI)

Electrical idle

Dynamic channel reconfiguration allowing you to change data rates and

protocols on-the-fly

Static equalization and pre-emphasis for superior signal integrity

150 mW per channel power consumption

Flexible clocking structure to support multiple protocols in a single transceiver

block

■

Cyclone IV GX devices offer dedicated hard IP for PCI Express (PIPE) (PCIe)

Gen 1:

■

×1, ×2, and ×4 lane configurations

End-point and root-port configurations

Up to 256-byte payload

One virtual channel

2 KB retry buffer

4 KB receiver (Rx) buffer

■

Cyclone IV GX devices offer a wide range of protocol support:

■

PCIe (PIPE) Gen 1 ×1, ×2, and ×4 (2.5 Gbps)

Gigabit Ethernet (1.25 Gbps)

CPRI (up to 3.072 Gbps)

XAUI (3.125 Gbps)

Triple rate serial digital interface (SDI) (up to 2.97 Gbps)

Serial RapidIO (3.125 Gbps)

Basic mode (up to 3.125 Gbps)

V-by-One (up to 3.0 Gbps)

DisplayPort (2.7 Gbps)

Serial Advanced Technology Attachment (SATA) (up to 3.0 Gbps)

OBSAI (up to 3.072 Gbps)

Cyclone IV Device Handbook,

Volume 1

March 2016 Altera Corporation

Chapter 1: Cyclone IV FPGA Device Family Overview

Device Resources

1–3

■

Up to 532 user I/Os

■

LVDS interfaces up to 840 Mbps transmitter (Tx), 875 Mbps Rx

Support for DDR2 SDRAM interfaces up to 200 MHz

Support for QDRII SRAM and DDR SDRAM up to 167 MHz

■

Up to eight phase-locked loops (PLLs) per device

Offered in commercial and industrial temperature grades

Device Resources

Table 1–1

lists Cyclone IV E device resources.

Table 1–1. Resources for the Cyclone IV E Device Family

EP4CE115

114,480

3,888

266

528

EP4CE10

EP4CE15

EP4CE22

EP4CE30

EP4CE40

EP4CE55

EP4CE75

75,408

2,745

200

426

EP4CE6

6,272

270

(1)

Resources

Logic elements (LEs)

Embedded memory

(Kbits)

Embedded 18 × 18

multipliers

General-purpose PLLs

Global Clock Networks

User I/O Banks

Maximum user I/O

Note to

Table 1–1:

10,320

414

179

15,408

504

343

22,320

594

153

28,848

594

532

39,600

1,134

116

532

55,856

2,340

154

374

179

(1) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver

pins and dedicated configuration pins are not included in the pin count.

March 2016

Altera Corporation

Cyclone IV Device Handbook,

Volume 1

1–4

Chapter 1: Cyclone IV FPGA Device Family Overview

Device Resources

Table 1–2

lists Cyclone IV GX device resources.

Table 1–2. Resources for the Cyclone IV GX Device Family

EP4CGX110

EP4CGX150

EP4CGX15

EP4CGX22

EP4CGX30

EP4CGX50

EP4CGX75

(1)

(2)

(3)

Resources

Logic elements (LEs)

Embedded memory (Kbits)

Embedded 18 × 18 multipliers

General purpose PLLs

Multipurpose PLLs

Global clock networks

High-speed transceivers

(6)

14,400

540

(5)

21,280

756

(5)

29,440

1,080

(5)

29,440

1,080

(4)

(5)

49,888

2,502

140

(4)

(5)

73,920

4,158

198

(4)

(5)

109,424

5,490

280

(4)

(5)

149,760

6,480

360

(4)

(5)

2.5

(7)

2.5

(7)

2.5

(7)

3.125

(8)

3.125

(8)

3.125

(8)

3.125

(8)

3.125

(8)

Transceiver maximum data rate

(Gbps)

PCIe (PIPE) hard IP blocks

User I/O banks

Maximum user I/O

Notes to

Table 1–2:

(9)

150

290

310

475

(1) Applicable for the F169 and F324 packages.

(2) Applicable for the F484 package.

(3) Only two multipurpose PLLs for F484 package.

(4) Two of the general purpose PLLs are able to support transceiver clocking. For more information, refer to the

Clock Networks and PLLs in

Cyclone IV Devices

chapter.

(5) You can use the multipurpose PLLs for general purpose clocking when they are not used to clock the transceivers. For more information, refer

to the

Clock Networks and PLLs in Cyclone IV Devices

chapter.

(6) If PCIe

1,

you can use the remaining transceivers in a quad for other protocols at the same or different data rates.

(7) Including one configuration I/O bank and two dedicated clock input I/O banks for HSSI reference clock input.

(8) Including one configuration I/O bank and four dedicated clock input I/O banks for HSSI reference clock input.

(9) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver

pins and dedicated configuration pins are not included in the pin count.

Cyclone IV Device Handbook,

Volume 1

March 2016 Altera Corporation

(3)

Package Matrix

Table 1–3

lists Cyclone IV E device package offerings.

Table 1–3. Package Offerings for the Cyclone IV E Device Family

(1),

Package

Size (mm)

Pitch (mm)

User I/O

Device

EP4CE6

EP4CE10

EP4CE15

EP4CE22

EP4CE30

EP4CE40

EP4CE55

EP4CE75

EP4CE115

E144

22 × 22

0.5

User I/O

(3)

(2)

Chapter 1: Cyclone IV FPGA Device Family Overview

Package Matrix

User I/O

—

532

374

426

528

(3)

LVDS

—

165

—

179

165

153

—

179

165

153

—

193

—

328

324

292

—

124

132

110

—

343

—

328

324

292

280

—

137

—

124

132

110

103

—

224

160

178

230

Notes to

Table 1–3:

(1) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground plane of your PCB. Use this exposed pad for electrical

connectivity and not for thermal purposes.

(2) Use the Pin Migration View window in Pin Planner of the Quartus II software to verify the pin migration compatibility when you perform device migration. For more information, refer to the

I/O

Management

chapter in volume 2 of the

Quartus II Handbook.

(3) This includes both dedicated and emulated LVDS pairs. For more information, refer to the

I/O Features in Cyclone IV Devices

chapter.

Cyclone IV Device Handbook,

Volume 1

LVDS

(3)

March 2016

Altera Corporation

M164

8×8

0.5

M256

9x9

0.5

U256

14 × 14

0.8

F256

17 × 17

1.0

F324

19 x 19

1.0

U484

19 × 19

0.8

F484

23 × 23

1.0

F780

29 × 29

1.0

1–5