EP7311-IB-90,EP7311-IB-90 pdf中文资料,EP7311-IB-90引脚图,EP7311-IB-90电路-Datasheet-电子工程世界

文档预览

EP7311 Data Sheet

FEATURES

ARM720T Processor

— ARM7TDMI CPU

— 8 KB of four-way set-associative cache

— MMU with 64-entry TLB

— Thumb code support enabled

Ultra low power

— 90 mW at 74 MHz typical

— 30 mW at 18 MHz typical

— 10 mW in the Idle State

— <1 mW in the Standby State

48 KB of on-chip SRAM

MaverickKey™ IDs

— 32-bit unique ID can be used for SDMI compliance

— 128-bit random ID

Dynamically programmable clock speeds of

18, 36, 49, and 74 MHz

High-performance,

Low-power, System-on-chip

with SDRAM & Enhanced

Digital Audio Interface

OVERVIEW

The Maverick™ EP7311 is designed for ultra-low-power

applications such as PDAs, smart cellular phones, and

industrial hand held information appliances. The core-logic

functionality of the device is built around an ARM720T

processor with 8 KB of four-way set-associative unified cache

and a write buffer. Incorporated into the ARM720T is an

enhanced memory management unit (MMU) which allows for

support of sophisticated operating systems like Linux

(cont.)

BLOCK DIAGRAM

Multimedia

Codec Port

Power

Management

EPB Bus

Clocks &

Timers

ARM720T

USER INTERFACE

ICE-JTAG

ARM7TDMI CPU Core

Interrupts,

PWM & GPIO

SERIAL PORTS

Serial

Interface

(2) UARTs

w/ IrDA

Internal Data Bus

8 KB

Cache

Boot

ROM

Write

Buffer

Bus

Bridge

MMU

Keypad&

Touch

Screen I/F

Memory Controller

MaverickKey

SRAM I/F

SDRAM I/F

On-chip SRAM

48 KB

LCD

Controller

MEMORY AND STORAGE



http://www.cirrus.com

MAR ‘11

DS506F2

EP7311

High-Performance, Low-Power System on Chip

FEATURES

(cont)

LCD controller

— Interfaces directly to a single-scan panel monochrome

STN LCD

— Interfaces to a single-scan panel color STN LCD with

minimal external glue logic

Full JTAG boundary scan and Embedded ICE



support

Integrated Peripheral Interfaces

— 32-bit SDRAM Interface up to 2 external banks

— 8/32/16-bit SRAM/FLASH/ROM Interface

— Multimedia Codec Port

— Two Synchronous Serial Interfaces (SSI1, SSI2)

— CODEC Sound Interface

— 8×8 Keypad Scanner

— 27 General Purpose Input/Output pins

— Dedicated LED flasher pin from the RTC

Internal Peripherals

— Two 16550 compatible UARTs

— IrDA Interface

— Two PWM Interfaces

— Real-time Clock

— Two general purpose 16-bit timers

— Interrupt Controller

— Boot ROM

Package

— 256-Ball PBGA

The fully static EP7311 is optimized for low power

dissipation and is fabricated on a 0.25 micron CMOS

process

Development Kits

— EDB7312: Development Kit with color STN LCD on

board.

Note:

* Use the EDB7312 Development Kit for all the EP73xx

devices.

OVERVIEW

(cont.)

The EP7311 is designed for low-power operation. Its core

operates at only 2.5 V, while its I/O has an operation range of

2.5 V–3.3 V. The device has three basic power states:

operating, idle and standby.

One of its notable features is MaverickKey unique IDs. These

are factory programmed IDs in response to the growing

concern over secure web content and commerce. With Internet

security playing an important role in the delivery of digital

media such as books or music, traditional software methods are

quickly becoming unreliable. The MaverickKey unique IDs

consist of two registers, one 32-bit series register and one

random 128-bit register that may be used by an OEM for an

authentication mechanism.

Simply by adding desired memory and peripherals to the

highly integrated EP7311 completes a low-power system

solution. All necessary interface logic is integrated on-chip.



DS506F2

EP7311

High-Performance, Low-Power System on Chip

Table of Contents

FEATURES

.........................................................................................................................................................2

OVERVIEW

..................................................................................................................................................................2

Processor Core - ARM720T ..................................................................................................................................6

Power Management ..............................................................................................................................................6

MaverickKey™ Unique ID .....................................................................................................................................6

Memory Interfaces .................................................................................................................................................6

Digital Audio Capability .........................................................................................................................................7

Universal Asynchronous Receiver/Transmitters (UARTs) .....................................................................................7

Multimedia Codec Port (MCP) ...............................................................................................................................7

CODEC Interface ..................................................................................................................................................8

SSI2 Interface ........................................................................................................................................................8

Synchronous Serial Interface ................................................................................................................................8

LCD Controller .......................................................................................................................................................8

Interrupt Controller ................................................................................................................................................9

Real-Time Clock ....................................................................................................................................................9

PLL and Clocking ..................................................................................................................................................9

DC-to-DC converter interface (PWM) ..................................................................................................................10

Timers .................................................................................................................................................................10

General Purpose Input/Output (GPIO) ................................................................................................................10

Hardware debug Interface ...................................................................................................................................10

Internal Boot ROM ...............................................................................................................................................10

Packaging ............................................................................................................................................................10

Pin Multiplexing ................................................................................................................................................... 11

System Design ....................................................................................................................................................12

ELECTRICAL SPECIFICATIONS ......................................................................................................13

Absolute Maximum Ratings .................................................................................................................................13

Recommended Operating Conditions .................................................................................................................13

DC Characteristics ..............................................................................................................................................13

Timings ...............................................................................................................................................15

Timing Diagram Conventions ....................................................................................................................15

Timing Conditions ......................................................................................................................................15

SDRAM Interface ................................................................................................................................................16

SDRAM Load Mode Register Cycle ..........................................................................................................17

SDRAM Burst Read Cycle .........................................................................................................................18

SDRAM Burst Write Cycle .........................................................................................................................19

SDRAM Refresh Cycle ..............................................................................................................................20

Static Memory ......................................................................................................................................................21

Static Memory Single Read Cycle .............................................................................................................22

Static Memory Single Write Cycle ..............................................................................................................23

Static Memory Burst Read Cycle ...............................................................................................................24

Static Memory Burst Write Cycle ...............................................................................................................25

SSI1 Interface ......................................................................................................................................................26

SSI2 Interface ......................................................................................................................................................27

LCD Interface ......................................................................................................................................................28

JTAG Interface ....................................................................................................................................................29

Packages ............................................................................................................................................30

256-Ball PBGA Package Characteristics ............................................................................................................30

256-Ball PBGA Package Specifications ....................................................................................................30

256-Ball PBGA Pinout (Top View) .............................................................................................................31

256-Ball PBGA Ball Listing ........................................................................................................................32

JTAG Boundary Scan Signal Ordering ................................................................................................................35

DS506F2



EP7311

High-Performance, Low-Power System on Chip

CONVENTIONS ................................................................................................................................. 40

Acronyms and Abbreviations .............................................................................................................................. 40

Units of Measurement ......................................................................................................................................... 40

General Conventions .......................................................................................................................................... 41

Pin Description Conventions ............................................................................................................................... 41

.................................................................................................................................................................. 41

Ordering Information ....................................................................................................................... 42

Environmental, Manufacturing, & Handling Information ............................................................. 42

Revision History .............................................................................................................................. 42



DS506F2

EP7311

High-Performance, Low-Power System on Chip

List of Figures

Figure 1. A Maximum EP7311 Based System ..............................................................................................................12

Figure 2. Legend for Timing Diagrams .........................................................................................................................15

Figure 3. SDRAM Load Mode Register Cycle Timing Measurement ............................................................................17

Figure 4. SDRAM Burst Read Cycle Timing Measurement ..........................................................................................18

Figure 5. SDRAM Burst Write Cycle Timing Measurement ..........................................................................................19

Figure 6. SDRAM Refresh Cycle Timing Measurement ................................................................................................20

Figure 7. Static Memory Single Read Cycle Timing Measurement ...............................................................................22

Figure 8. Static Memory Single Write Cycle Timing Measurement ...............................................................................23

Figure 9. Static Memory Burst Read Cycle Timing Measurement ................................................................................24

Figure 10. Static Memory Burst Write Cycle Timing Measurement ..............................................................................25

Figure 11. SSI1 Interface Timing Measurement ...........................................................................................................26

Figure 12. SSI2 Interface Timing Measurement ...........................................................................................................27

Figure 13. LCD Controller Timing Measurement ..........................................................................................................28

Figure 14. JTAG Timing Measurement .........................................................................................................................29

Figure 15. 256-Ball PBGA Package ..............................................................................................................................30

List of Tables

Table A. Power Management Pin Assignments ..............................................................................................................6

Table B. Static Memory Interface Pin Assignments ........................................................................................................6

Table C. SDRAM Interface Pin Assignments ..................................................................................................................7

Table D. Universal Asynchronous Receiver/Transmitters Pin Assignments ...................................................................7

Table E. MCP Interface Pin Assignments .......................................................................................................................7

Table F. CODEC Interface Pin Assignments ..................................................................................................................8

Table G. SSI2 Interface Pin Assignments .......................................................................................................................8

Table H. Serial Interface Pin Assignments .....................................................................................................................8

Table I. LCD Interface Pin Assignments .........................................................................................................................8

Table J. Keypad Interface Pin Assignments ...................................................................................................................9

Table K. Interrupt Controller Pin Assignments ................................................................................................................9

Table L. Real-Time Clock Pin Assignments ....................................................................................................................9

Table M. PLL and Clocking Pin Assignments .................................................................................................................9

Table N. DC-to-DC Converter Interface Pin Assignments ............................................................................................10

Table O. General Purpose Input/Output Pin Assignments ...........................................................................................10

Table P. Hardware Debug Interface Pin Assignments ..................................................................................................10

Table Q. LED Flasher Pin Assignments .......................................................................................................................10

Table R. MCP/SSI2/CODEC Pin Multiplexing ...............................................................................................................11

Table S. Pin Multiplexing ..............................................................................................................................................11

Table T. 256-Ball PBGA Ball Listing .............................................................................................................................32

Table U. JTAG Boundary Scan Signal Ordering ...........................................................................................................35

Table V. Acronyms and Abbreviations ..........................................................................................................................40

Table W. Unit of Measurement .....................................................................................................................................40

Table X. Pin Description Conventions ..........................................................................................................................41

DS506F2



型号	EP7311-IB-90	EP7311-CV	EP7311-IB	EP7311-IV
描述	Processors - Application Specialized IC Ultra Low PWR Hi Perf SOC w/LCD	Processors - Application Specialized IC Ultra Low PWR Hi Perf SOC w/LCD	Processors - Application Specialized IC Ultra Low PWR Hi Perf SOC w/LCD	Processors - Application Specialized IC Ultra Low PWR Hi Perf SOC w/LCD
是否Rohs认证	不符合	不符合	不符合	不符合
厂商名称	Cirrus Logic(凌云半导体)	Cirrus Logic(凌云半导体)	Cirrus Logic(凌云半导体)	Cirrus Logic(凌云半导体)
零件包装代码	BGA	QFP	BGA	QFP
包装说明	BGA,	LFQFP,	BGA,	LFQFP,
针数	256	208	256	208
Reach Compliance Code	unknown	unknown	unknown	unknown
具有ADC	YES	YES	YES	YES
地址总线宽度	28	28	28	28
位大小	32	32	32	32
最大时钟频率	13 MHz	13 MHz	13 MHz	13 MHz
DAC 通道	NO	NO	NO	NO
DMA 通道	NO	NO	NO	NO
外部数据总线宽度	32	32	32	32
JESD-30 代码	S-PBGA-B256	S-PQFP-G208	S-PBGA-B256	S-PQFP-G208
JESD-609代码	e0	e0	e0	e0
长度	17 mm	28 mm	17 mm	28 mm
湿度敏感等级	3	3	3	3
I/O 线路数量	27	27	27	27
端子数量	256	208	256	208
最高工作温度	85 °C	70 °C	85 °C	85 °C
最低工作温度	-40 °C	-	-40 °C	-40 °C
PWM 通道	YES	YES	YES	YES
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	BGA	LFQFP	BGA	LFQFP
封装形状	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	GRID ARRAY	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	225	225	225	225
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.8 mm	1.6 mm	1.8 mm	1.6 mm
速度	90 MHz	74 MHz	74 MHz	74 MHz
最大供电电压	2.7 V	2.7 V	2.7 V	2.7 V
最小供电电压	2.3 V	2.3 V	2.3 V	2.3 V
标称供电电压	2.5 V	2.5 V	2.5 V	2.5 V
表面贴装	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL
端子面层	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD
端子形式	BALL	GULL WING	BALL	GULL WING
端子节距	1 mm	0.5 mm	1 mm	0.5 mm
端子位置	BOTTOM	QUAD	BOTTOM	QUAD
处于峰值回流温度下的最长时间	30	30	30	30
宽度	17 mm	28 mm	17 mm	28 mm
uPs/uCs/外围集成电路类型	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC