eGaN® FET DATASHEET
EPC2110
EPC2110 – Dual Common-Source
Enhancement-Mode GaN Power Transistor
V
DS
, 120 V
R
DS(on)
, 110 mΩ
I
D
, 3.4 A
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low R
DS(on)
, while its lateral device structure and majority carrier diode provide exceptionally low Q
G
and zero Q
RR
. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
EFFICIENT POWER CONVERSION
HAL
Maximum Ratings of Q1 & Q2
PARAMETER
V
DS
I
D
V
GS
T
J
T
STG
Drain-to-Source Voltage (Continuous)
Continuous (T
A
= 25°C, R
θJA
= 52°C/W)
Pulsed (25°C, T
PULSE
= 300 µs)
Gate-to-Source Voltage
Gate-to-Source Voltage
Operating Temperature
Storage Temperature
VALUE
120
3.4
20
6
–4
–40 to 150
–40 to 150
UNIT
V
A
V
°C
EPC2110 eGaN® FETs are supplied only in
passivated die form with solder bumps
Die Size: 1.35 mm x 1.35 mm
Applications
• Ultra High Frequency DC-DC Conversion
• Wireless Power Transfer
• Synchronous Rectification
Benefits
• Ultra High Efficiency
• Ultra Low R
DS(on)
• Ultra Low Q
G
• Ultra Small Footprint
www.epc-co.com/epc/Products/eGaNFETsandICs/EPC2110.aspx
Thermal Characteristics of Q1 & Q2
PARAMETER
R
0JC
R
0JB
R
0JA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Board
Thermal Resistance, Junction-to-Ambient (Note 1)
TYP
3
25
81
UNIT
°C/W
Note 1: R
θJA
is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See
http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details
PARAMETER
BV
DSS
I
DSS
I
GSS
V
GS(TH)
R
DS(on)
V
SD
Drain-Source Leakage
Static Characteristics of Q1 & Q2 (T
J
= 25˚C unless otherwise stated)
TEST CONDITIONS
V
GS
= 0 V, I
D
= 0.3 mA
V
DS
= 96 V, V
GS
= 0 V
V
GS
= 5 V
V
GS
= -4 V
V
DS
= V
GS
, I
D
= 0.7 mA
V
GS
= 5 V, I
D
= 4 A
I
S
= 0.5 A, V
GS
= 0 V
MIN
120
TYP
0.01
0.05
0.01
MAX
0.25
1
0.25
2.5
110
UNIT
V
mA
mA
mA
V
mΩ
V
Drain-to-Source Voltage
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Threshold Voltage
Drain-Source On Resistance
Source-Drain Forward Voltage
0.8
1.4
80
1.9
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| COPYRIGHT 2018 |
| 1
eGaN® FET DATASHEET
3
2
9
8
EPC2110
D1
Q1
G1
D2
Q2
G2
1
7
S
4
5
6
EPC2110 – Detailed Schematic
Note: The EPC2110 can be connected in parallel or used as independent FETs with common source.
Dynamic Characteristics of Q1 & Q2 (T
J
= 25˚C unless otherwise stated)
PARAMETER
TEST CONDITIONS
C
ISS
C
RSS
C
OSS
C
OSS(ER)
C
OSS(TR)
R
G
Q
G
Q
GS
Q
GD
Q
G(TH)
Q
OSS
Q
RR
Input Capacitance
Reverse Transfer Capacitance
Output Capacitance
Effective Output Capacitance, Energy Related (Note 2)
Effective Output Capacitance, Time Related (Note 3)
Gate Resistance
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Gate Charge at Threshold
Output Charge
Source-Drain Recovery Charge
V
DS
= 60 V, V
GS
= 0 V
V
DS
= 60 V, I
D
= 4 A
V
DS
= 60 V, V
GS
= 5 V, I
D
= 4 A
V
DS
= 0 to 60 V, V
GS
= 0 V
V
DS
= 60 V, V
GS
= 0 V
MIN
TYP
85
1
45
54
67
0.6
0.8
0.25
0.18
0.16
4
0
MAX
100
70
UNIT
pF
Ω
1.1
nC
6
Note 2: C
OSS(ER)
is a fixed capacitance that gives the same stored energy as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.
Note 3: C
OSS(TR)
is a fixed capacitance that gives the same charging time as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.
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| COPYRIGHT 2018 |
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eGaN® FET DATASHEET
Figure 1 (Q1 & Q2): Typical Output Characteristics at 25°C
20
20
25˚C
125˚C
V
DS
= 3 V
EPC2110
Figure 2 (Q1 & Q2): Transfer Characteristics
15
15
I
D
–
Drain Current (A)
10
V
GS
= 5 V
V
GS
= 4 V
5
V
GS
= 3 V
V
GS
= 2 V
0
I
D
–
Drain Current (A)
10
5
0
0.5
V
DS
–
Drain-to-Source Voltage (V)
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
V
GS
– Gate-to-Source Voltage (V)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Figure 3 (Q1 & Q2): R
DS(on)
vs. V
GS
for Various Drain Currents
300
300
Figure 4 (Q1 & Q2): R
DS(on)
vs. V
GS
for Various Temperatures
R
DS(on)
– Drain-to-Source Resistance (m )
R
DS(on)
– Drain-to-Source Resistance (m )
25˚C
125˚C
I
D
= 4 A
200
200
I
D
= 1 A
I
D
= 2A
I
D
= 4 A
I
D
= 8 A
100
100
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
V
GS
– Gate-to-Source Voltage (V)
2.0
2.5
V
GS
– Gate-to-Source Voltage (V)
3.0
3.5
4.0
4.5
5.0
Figure 5a (Q1 & Q2): Capacitance (Linear Scale)
150
100
C
OSS
= C
GD
+ C
SD
C
ISS
= C
GD
+ C
GS
C
RSS
= C
GD
Figure 5b (Q1 & Q2): Capacitance (Log Scale)
Capacitance (pF)
Capacitance (pF)
100
10
C
OSS
= C
GD
+ C
SD
C
ISS
= C
GD
+ C
GS
C
RSS
= C
GD
50
1
0
0
20
40
60
80
100
120
0.1
0
20
40
60
80
100
120
V
DS
– Drain-to-Source Voltage (V)
V
DS
– Drain-to-Source Voltage (V)
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| COPYRIGHT 2018 |
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eGaN® FET DATASHEET
Figure 6a: Output Charge and C
OSS
Stored Energy
Energy
6 (Q1 & Q2): Output Charge and C
OSS
Stored
Figure 7 (Q1 & Q2): Gate Charge
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
120
5
I
D
= 4 A
V
DS
= 60 V
EPC2110
7
6
5
4
3
2
1
0
V
GS
– Gate-to-Source Voltage (V)
E
OSS
–
C
OSS
Stored Energy ( J)
4
Q
OSS
–
Output Charge (nC)
3
2
1
0
20
40
60
80
100
0
V
DS
– Drain-to-Source Voltage (V)
0
0.2
Q
G
– Gate Charge (pC)
0.4
0.6
0.8
1
Figure 8: Reverse Drain-Source Characteristics
20
2.0
Figure 9 (Q1 & Q2):
Normalized On-State Resistance vs. Temperature
Normalized On-State Resistance R
DS(on)
I
SD
– Source-to-Drain Current (A)
15
25˚C
125˚C
3
V
DS
= 0 V
GS
1.8
1.6
1.4
1.2
1.0
0.8
I
D
= 4 A
V
GS
= 5 V
10
5
0
0
0.5
1.0
V
SD
– Source-to-Drain Voltage (V)
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
25
T
J
– Junction Temperature (°C)
50
75
100
125
150
Figure 10 (Q1 & Q2):
Normalized Threshold Voltage vs. Temperature
1.40
1.30
Normalized Threshold Voltage
1.20
1.10
1.00
0.90
0.80
0.70
0.60
0
I
D
= 0.7 mA
25
T
J
– Junction Temperature (°C)
50
75
100
125
150
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| COPYRIGHT 2018 |
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eGaN® FET DATASHEET
EPC2110
Figure 11a (Q1 & Q2): Transient Thermal Response Curves (Junction-to-Board)
Z
θJB
, Normalized Thermal Impedance
1
Duty Cycle:
0.5
0.1
0.1
0.05
0.02
0.01
0.01
Single Pulse
10
-4
10
-3
10
-2
P
DM
t
1
t
2
0.001
10
-5
Notes:
Single
= t /t
Duty Factor: D
Pulse
2
1
Peak T
J
= P
DM
x Z
θJB
x R
θJB
+ T
B
10
-1
1
10
1
t
p
, Rectangular Pulse Duration, seconds
Figure 11b (Q1 & Q2): Transient Thermal Response Curves (Junction-to-Case)
Z
θJC
, Normalized Thermal Impedance
1
Duty Cycle:
0.5
0.2
0.1
0.1
0.05
P
DM
t
1
t
2
0.02
0.01
0.01
Single Pulse
0.001
10
-6
10
-5
10
-4
10
-3
Notes:
Single Pulse
Duty Factor: D = t
1
/t
2
Peak T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
-2
10
-1
1
t
p
, Rectangular Pulse Duration, seconds
Figure 12 (Q1 & Q2): Safe Operating Area
100
I
D
– Drain Current (A)
10
Limited by R
DS(on)
1
Pulse Width
1
100 µs
ms
100 µs
10 µs
1
10
100
1000
0.1
0.1
V
DS
– Drain-Source Voltage (V)
T
J
= Max rated, T
C
= +25°C, Single pulse
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| COPYRIGHT 2018 |
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