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2016.05.04

Enhanced Configuration (EPC) Devices Datasheet

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CF52002

Supported Devices

Table 1: Altera EPC Devices

Device

Memory Size (bits)

On-Chip

ISP Support

Decompres‐

sion Support

Cascading

Support

Reprogram‐

mable

Recommend

Operating Voltage

(V)

EPC4

EPC8

EPC16

4,194,304

8,388,608

16,777,216

Yes

3.3

Features

EPC devices offer the following features:

• Single-chip configuration solution for Altera

ACEX



1K, APEX



20K (including APEX 20K, APEX

20KC, and APEX 20KE), APEX II, Arria



GX, Cyclone



, Cyclone II, FLEX



10K (including FLEX

10KE and FLEX 10KA), Mercury



, Stratix



II, and Stratix II GX devices

• Contains 4-, 8-, and 16-Mb flash memories for configuration data storage

• On-chip decompression feature almost doubles the effective configuration density

• Standard flash die and a controller die combined into single stacked chip package

• External flash interface supports parallel programming of flash and external processor access to

unused portions of memory

• Flash memory block or sector protection capability using the external flash interface

• Supported in EPC4 and EPC16 devices

• Page mode support for remote and local reconfiguration with up to eight configurations for the entire

system

• Compatible with Stratix series remote system configuration feature

• Supports byte-wide configuration mode fast passive parallel (FPP) with an 8-bit data output per DCLK

cycle

• Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs

• Pin selectable 2-ms or 100-ms power-on reset (POR) time

• Configuration clock supports programmable input source and frequency synthesis

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trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html.

Altera warrants performance

of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,

product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

www.altera.com

101 Innovation Drive, San Jose, CA 95134

Functional Description

CF52002

2016.05.04

• Multiple configuration clock sources supported (internal oscillator and external clock input pin)

• External clock source with frequencies up to 100 MHz

• Internal oscillator defaults to 10 MHz and you can program the internal oscillator for higher frequen‐

cies of 33, 50, and 66 MHz

• Clock synthesis supported using user programmable divide counter

• Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra FineLine BGA (UFBGA)

packages

• Vertical migration between all devices supported in the 100-pin PQFP package

• Supply voltage of 3.3 V (core and I/O)

• Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification

• Supports ISP using Jam Standard Test and Programming Language (STAPL)

• Supports JTAG boundary scan

• The nINIT_CONF pin allows private JTAG instruction to start FPGA configuration

• Internal pull-up resistor on the nINIT_CONF pin always enabled

• User programmable weak internal pull-up resistors on nCS and OE pins

• Internal weak pull-up resistors on external flash interface address and control lines, bus hold on data

lines

• Standby mode with reduced power consumption

Note:

For more information about FPGA configuration schemes and advanced features, refer to the

configuration chapter in the appropriate device handbook.

Functional Description

The Altera EPC device is a single device with high speed and advanced configuration solution for high-

density FPGAs. The core of an EPC device is divided into two major blocks—a configuration controller

and a flash memory. The flash memory is used to store configuration data for systems made up of one or

more than one Altera FPGAs. Unused portions of the flash memory can be used to store processor code

or data that can be accessed using the external flash interface after the FPGA configuration is complete.

Altera Corporation

Enhanced Configuration (EPC) Devices Datasheet

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CF52002

2016.05.04

Functional Description

Table 2: Supported EPC devices required to configure an ACEX 1K, APEX 1K, APEX 20K, APEX 20KC, APEX

20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 10KA, FLEX 10KE, Stratix, Stratix GX, Stratix II,

Stratix II GX, or Mercury device.

Device Family

Device

Data Size (Bits)

(1)

EPC Devices

(2)

EPC4

EPC8

EPC16

EP1AGX20C

EP1AGX35C

EP1AGX35D

EP1AGX50C

Arria GX

EP1AGX50D

EP1AGX60C

EP1AGX60D

EP1AGX60E

EP1AGX90E

EP1S10

EP1S20

EP1S25

Stratix

EP1S30

EP1S40

EP1S60

EP1S80

EP1SGX10

Stratix GX

EP1SGX25

EP1SGX40

EP2S15

EP2S30

Stratix II

EP2S60

EP2S90

EP2S130

EP2S180

9,640,672

—

16,951,824

25,699,104

3,534,640

5,904,832

7,894,144

10,379,368

12,389,632

17,543,968

23,834,032

3,534,640

7,894,144

12,389,632

4,721,544

9,640,672

16,951,824

25,699,104

37,325,760

49,814,760

—

(1)

The Raw Binary File (

.rbf

) sizes are used to determine the data size for each device.

Altera Corporation

Enhanced Configuration (EPC) Devices Datasheet

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Functional Description

CF52002

2016.05.04

Device Family

Device

Data Size (Bits)

(1)

EPC Devices

(2)

EPC4

EPC8

EPC16

EP2SGX30C

EP2SGX30D

EP2SGX60C

Stratix II

EP2SGX60D

EP2SGX60E

EP2SGX90E

EP2SGX90F

EP2SGX130G

EP1C3

EP1C4

Cyclone

EP1C6

EP1C12

EP1C20

EP2C5

EP2C8

Cyclone II

EP2C20

EP2C35

EP2C50

EP2C70

EP1K10

ACEX 1K

EP1K30

EP1K50

EP1K100

EP20K100

APEX 20K

EP20K200

EP20K400

9,640,672

16,951,824

25,699,104

37,325,760

627,376

924,512

1,167,216

2,326,528

3,559,608

1,223,980

1,983,792

3,930,986

7,071,234

9,122,148

10,249,694

159,160

473,720

784,184

1,335,720

993,360

1,950,800

3,880,720

—

(1)

(2)

The Raw Binary File (

.rbf

) sizes are used to determine the data size for each device.

These values are calculated with the compression feature of the EPC device enabled.

Enhanced Configuration (EPC) Devices Datasheet

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Altera Corporation

CF52002

2016.05.04

Functional Description

Device Family

Device

Data Size (Bits)

(1)

EPC Devices

(2)

EPC4

EPC8

EPC16

EP20K200C

APEX 20KC

EP20K400C

EP20K600C

EP20K1000C

EP20K30E

EP20K60E

EP20K100E

EP20K160E

APEX 20KE

EP20K200E

EP20K300E

EP20K400E

EP20K600E

EP20K1000E

EP20K1500E

EP2A15

APEX II

EP2A25

EP2A40

EP2A70

1,968,016

3,909,776

5,673,936

8,960,016

354,832

648,016

1,008,016

1,524,016

1,968,016

2,741,616

3,909,776

5,673,936

8,960,016

12,042,256

4,358,512

6,275,200

9,640,528

17,417,088

—

Table 3: Supported Flash Memory for EPC Devices

Device Family

Grade

Package

Flash Memory

Leaded

Lead-Fee

EPC4

EPC8

Commercial

Industrial

Commercial/Industrial

PQFP 100

Intel or Micron

Intel or Sharp

Intel or Micron

Intel

(1)

(2)

The Raw Binary File (

.rbf

) sizes are used to determine the data size for each device.

These values are calculated with the compression feature of the EPC device enabled.

Altera Corporation

Enhanced Configuration (EPC) Devices Datasheet

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