The EPC9010 development board is a 100 V maximum device volt-
age, 7 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2016 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2016
eGaN
FET by in-
cluding all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9010 development board is 2” x 1.5” and contains two
EPC2016
eGaN
FET in a half bridge configuration using Texas
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER
V
DD
V
IN
V
OUT
I
OUT
V
PWM
Gate Drive Input Supply Range
Bus Input Voltage Range
Switch Node Output Voltage
Switch Node Output Current
PWM Logic Input Voltage Threshold
Minimum ‘High’ State Input Pulse Width
Minimum ‘Low’ State Input Pulse Width
Input ‘High’
Input ‘Low’
VPWM rise and fall time < 10ns
VPWM rise and fall time < 10ns
3.5
0
60
200
#
CONDITIONS
MIN
7
MAX
12
70*
100
7*
6
1.5
www.epc-co.com
Instruments LM5113 gate driver, supply and bypass capacitors.
The board contains all critical components and layout for optimal
switching performance. There are also various probe points to
facilitate simple waveform measurement and efficiency calculation.
A complete block diagram of the circuit is given in Figure 1.
For more information on the EPC2016s
eGaN
FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
UNITS
V
V
V
A
V
V
ns
ns
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
Quick Start Procedure
Development board EPC9010 is easy to set up to evaluate the performance of the EPC2016
eGaN
FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1.
2.
3.
4.
5.
6.
7.
8.
With power off, connect the input power supply bus to +V
IN
(J5, J6) and ground / return to –V
IN
(J7, J8).
With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
With power off, connect the gate drive input to +V
DD
(J1, Pin-1) and ground return to –V
DD
(J1, Pin-2).
With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on V
OUT
).
Turn on the controller / PWM input source and probe switching node to see switching operation.
Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
THERMAL CONSIDERATIONS
The EPC9010 development board showcases the EPC2016
eGaN
FET. Although the electrical performance surpasses that for traditional silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9010 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9010 development board does not have any current or thermal protection on board.
7 V – 12 V
V
DD
Gate Drive
Regulator
Logic and
Dead-time
Adjust
Gate Drive Supply
Half-Bridge with Bypass
V
DD
Supply
–
0, 100
V
IN
LM5113
Gate
Driver
OUT
+
Gate Drive Supply
(Note Polarity)
PWM
Input
A
I
IN
Switch Node
+
–
<
70 V
–
(For E ciency
Measurement)
V
IN
V
+
V
IN
Supply
External Circuit
Figure 1: Block Diagram of EPC9010 Development Board
