Section I. MAX II Device
Family Data Sheet
This section provides designers with the data sheet specifications for
MAX
®
II devices. The chapters contain feature definitions of the internal
architecture, Joint Test Action Group (JTAG) and in-system
programmability (ISP) information, DC operating conditions, AC timing
parameters, and ordering information for MAX II devices.
This section includes the following chapters:
■
■
■
■
■
■
Chapter 1. Introduction
Chapter 2. MAX II Architecture
Chapter 3. JTAG & In-System Programmability
Chapter 4. Hot Socketing & Power-On Reset in MAX II Devices
Chapter 5. DC & Switching Characteristics
Chapter 6. Reference & Ordering Information
Revision History
The table below shows the revision history for
Chapters 1
through
6.
Chapter(s)
1
Date/Version
August 2006, v1.5
July 2006, v1.4
June 2005, v1.3
Changes Made
Minor update to features list.
Minor updates to tables.
Updated timing numbers in Table 1-1.
December 2004, v1.2 Updated timing numbers in Table 1-1.
June 2004, v1.1
2
August 2006, v1.6
Updated timing numbers in Table 1-1.
Updated functional description and I/O
structure sections.
Altera Corporation
Section I–1
Preliminary
Revision History
MAX II Device Handbook
Chapter(s)
Date/Version
July 2006, v1.5
February 2006, v1.4
Changes Made
Minor content and table updates.
●
●
●
●
Updated
“LAB Control Signals”
section.
Updated
“Clear & Preset Logic Control”
section.
Updated
“Internal Oscillator”
section.
Updated
Table 2–5.
August 2005, v1.3
Removed Note 2 from Table 2-7.
December 2004, v1.2 Added a paragraph to page 2-15.
June 2004, v1.1
3
Added CFM acronym. Corrected Figure
2-19.
Added text and Table 3-4.
June 2005, v1.3
December 2004, v1.2 Updated text on pages 3-5 to 3-8.
June 2004, v1.1
4
Corrected Figure 3-1. Added CFM
acronym.
●
●
●
February 2006, v1.4
Updated
“MAX II Hot-Socketing
Specifications”
section.
Updated
“AC & DC Specifications”
section.
Updated
“Power-On Reset Circuitry”
section.
June 2005, v1.3
Updated AC and DC specifications on page
4-2.
December 2004, v1.2 Added content to Power-Up Characteristics
section.
Updated Figure 4-5.
June 2004, v1.1
5
July 2006, v. 1.7
February 2006, v1.6
Corrected Figure 4-2.
Minor content and table updates.
●
●
●
Updated
“External Timing I/O Delay
Adders”
section.
Updated
Table 5–29.
Updated
Table 5–30.
November 2005, v1.5 Updated Tables 5-2, 5-4, and 5-12.
August 2005, v1.4
Updated Figure 5-1.
Updated Tables 5-13, 5-16, and 5-26.
Removed Note 1 from Table 5-12.
Section I–2
Preliminary
Altera Corporation
Revision History
Chapter(s)
Date/Version
June 2005, v1.3
Changes Made
Updated the R
PULLUP
parameter in
Table 5-4.
Added Note 2 to Tables 5-8 and 5-9.
Updated Table 5-13.
Added Output Drive Characteristics section.
Added I
2
C mode and Notes 5 and 6 to
Table 5-14.
Updated timing values to Tables 5-14
through 5-33.
December 2004, v1.2 Updated timing tables 5-2, 5-4, 5-12, and
Tables 15-14 through 5-34.
Table 5-31 is new.
June 2004, v1.1
6
October 2006, v1.2
June 2005, v1.1
Updated timing Tables 5-15 through 5-32.
Updated Figure 6-1.
Removed Dual Marking section.
Altera Corporation
I–3
Preliminary
Revision History
MAX II Device Handbook
I–4
Preliminary
Altera Corporation
Chapter 1. Introduction
MII51001-1.5
Introduction
The MAX
®
II family of instant-on, non-volatile CPLDs is based on a
0.18-µm, 6-layer-metal-flash process, with densities from 240 to 2,210
logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile
storage of 8 Kbits. MAX II devices offer high I/O counts, fast
performance, and reliable fitting versus other CPLD architectures.
Featuring MultiVolt™ core, a user flash memory (UFM) block, and
enhanced in-system programmability (ISP), MAX II devices are designed
to reduce cost and power while providing programmable solutions for
applications such as bus bridging, I/O expansion, power-on reset (POR)
and sequencing control, and device configuration control.
The following shows the main sections of the MAX II CPLD Family Data
Sheet:
Section
Page
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
Global Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
User Flash Memory Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
MultiVolt Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28
IEEE Std. 1149.1 (JTAG) Boundary Scan Support . . . . . . . . . . 3–1
In System Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Hot Socketing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Power-On Reset Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Timing Model & Specifications . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
Altera Corporation
August 2006
Core Version a.b.c variable
1–1
Preliminary
