Section I. MAX II Device
Family Data Sheet
This section provides designers with the data sheet specifications for
MAX
®
II devices. The chapters contain feature definitions of the internal
architecture, Joint Test Action Group (JTAG) and in-system
programmability (ISP) information, DC operating conditions, AC timing
parameters, and ordering information for MAX II devices.
This section includes the following chapters:
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■
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Chapter 1. Introduction
Chapter 2. MAX II Architecture
Chapter 3. JTAG and In-System Programmability
Chapter 4. Hot Socketing and Power-On Reset in MAX II Devices
Chapter 5. DC and Switching Characteristics
Chapter 6. Reference and Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information
about when each chapter was updated, refer to the Chapter Revision
Dates section, which appears in the complete handbook.
Altera Corporation
Section I–1
Revision History
MAX II Device Handbook
I–2
Altera Corporation
Chapter 1. Introduction
MII51001-1.7
Introduction
The MAX
®
II family of instant-on, non-volatile CPLDs is based on a
0.18-µm, 6-layer-metal-flash process, with densities from 240 to 2,210
logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile
storage of 8 Kbits. MAX II devices offer high I/O counts, fast
performance, and reliable fitting versus other CPLD architectures.
Featuring MultiVolt core, a user flash memory (UFM) block, and
enhanced in-system programmability (ISP), MAX II devices are designed
to reduce cost and power while providing programmable solutions for
applications such as bus bridging, I/O expansion, power-on reset (POR)
and sequencing control, and device configuration control.
The MAX II CPLD has the following features:
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Features
■
■
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Low-cost, low-power CPLD
Instant-on, non-volatile architecture
Standby current as low as 29 µA
Provides fast propagation delay and clock-to-output times
Provides four global clocks with two clocks available per logic array
block (LAB)
UFM block up to 8 Kbits for non-volatile storage
MultiVolt core enabling external supply voltages to the device of
either 3.3 V/2.5 V or 1.8 V
MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic
levels
Bus-friendly architecture including programmable slew rate, drive
strength, bus-hold, and programmable pull-up resistors
Schmitt triggers enabling noise tolerant inputs (programmable per
pin)
Fully compliant with the Peripheral Component Interconnect Special
Interest Group (PCI SIG)
PCI Local Bus Specification, Revision 2.2
for
3.3-V operation at 66 MHz
Supports hot-socketing
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)
circuitry compliant with IEEE Std. 1149.1-1990
ISP circuitry compliant with IEEE Std. 1532
Altera Corporation
December 2007
1–1
Features
Table 1–1
shows the MAX II family features.
Table 1–1. MAX II Family Features
Feature
LEs
Typical Equivalent
Macrocells
Equivalent Macrocell
Range
UFM Size (bits)
Maximum User I/O pins
t
PD1
(ns)
(1)
f
CNT
(MHz)
(2)
t
SU
(ns)
t
CO
(ns)
Notes to
Table 1–1:
(1)
(2)
t
PD1
represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and
combinational logic implemented in a single LUT and LAB that is adjacent to the output pin.
The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay
will run faster than this number.
EPM240
EPM570
EPM240G EPM570G
240
192
570
440
EPM1270
EPM1270G
1,270
980
EPM2210
EPM2210G
2,210
1,700
EPM240Z
240
192
128 to 240
8,192
80
7.5
152
2.3
6.5
EPM570Z
570
440
240 to 570
8,192
160
9.0
152
2.2
6.7
128 to 240 240 to 570 570 to 1,270 1,270 to 2,210
8,192
80
4.7
304
1.7
4.3
8,192
160
5.4
304
1.2
4.5
8,192
212
6.2
304
1.2
4.6
8,192
272
7.0
304
1.2
4.6
f
For more information about equivalent macrocells, refer to the
MAX II
Logic Element to Macrocell Conversion Methodology
white paper.
MAX II and MAX IIG devices are available in three speed grades: –3, –4,
and –5, with –3 being the fastest. Similarly, MAX IIZ devices are available
in two speed grades: –6, –7, with –6 being faster. These speed grades
represent the overall relative performance, not any specific timing
parameter. For propagation delay timing numbers within each speed
grade and density, refer to the
DC and Switching Characteristics
chapter in
the
MAX II Device Handbook.
1–2
MAX II Device Handbook, Volume 1
Core Version a.b.c variable
Altera Corporation
December 2007
Introduction
Table 1–2
shows MAX II device speed-grade offerings.
Table 1–2. MAX II Speed Grades
Speed Grade
Device
–3
EPM240
EPM240G
EPM570
EPM570G
EPM1270
EPM1270G
EPM2210
EPM2210G
EPM240Z
EPM570Z
–4
v
v
v
v
—
—
–5
v
v
v
v
—
—
–6
—
—
—
—
–7
—
—
—
—
v
v
v
v
—
—
v
v
v
v
MAX II devices are available in space-saving FineLine BGA, Micro
FineLine BGA, and thin quad flat pack (TQFP) packages (refer to
Tables 1–3
and
1–4).
MAX II devices support vertical migration within the
same package (for example, you can migrate between the EPM570,
EPM1270, and EPM2210 devices in the 256-pin FineLine BGA package).
Vertical migration means that you can migrate to devices whose
dedicated pins and JTAG pins are the same and power pins are subsets or
supersets for a given package across device densities. The largest density
in any package has the highest number of power pins; you must lay out
for the largest planned density in a package to provide the necessary
power pins for migration. For I/O pin migration across densities, cross
reference the available I/O pins using the device pin-outs for all planned
densities of a given package type to identify which I/O pins can be
migrated. The Quartus
®
II software can automatically cross-reference and
place all pins for you when given a device migration list.
Altera Corporation
December 2007
1–3
MAX II Device Handbook, Volume 1
