EPS13D2C1HE-66.000M TR
Series
RoHS Compliant (Pb-free) 3.3V 4 Pad 5mm x 7mm
Ceramic SMD LVCMOS Programmable Spread
Spectrum Oscillator
Frequency Stability
±100ppm Maximum over Operating Temperature of
-20°C to +70°C
Duty Cycle
50 ±10%
RoHS
Pb
Packaging Options
Tape & Reel
EPS13D2 C 1 H E -66.000M TR
Nominal Frequency
66.000MHz
Spread Spectrum
±1.50% Center Spread
Output Control Function
Tri-State
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Stability
66.000MHz
±100ppm Maximum over Operating Temperature of -20°C to +70°C (Inclusive of all conditions: Frequency
Stability over the Operating Temperature Range, Supply Voltage Change, Output Load Change, First Year
Aging at 25°C, Shock, and Vibration.)
±5ppm First Year Maximum
3.3Vdc ±0.3Vdc
-0.5Vdc to +7.0Vdc
30mA Maximum (Unloaded; Vdd=3.3Vdc)
Vdd-0.4Vdc Minimum (IOH=-8mA)
0.4Vdc Maximum (IOL=+8mA)
2.7nSec Maximum (Measured at 20% to 80% of Waveform)
50 ±10% (Measured at 50% of Waveform)
15pF Maximum
CMOS
Tri-State (High Impedance Internal Pull Down Resistor of 100kOhms Typical on Pad 3, Internal Pull Up
Resistor of 100kOhms Typical on Pad 1)
70% of Vdd Minimum or No Connection to Enable Output, 30% of Vdd Maximum to Disable Output
350nSec Maximum
350nSec Maximum
20mA Maximum (Unloaded; Pad 1=Ground; Vdd=3.3Vdc)
±1.50% Center Spread
30kHz Minimum, 31.5kHz Typical, 33kHz Maximum
400pSec Maximum (Cycle to Cycle; Spread Spectrum-On; Vdd=3.3Vdc)
10mSec Maximum
-55°C to +125°C
Aging at 25°C
Supply Voltage
Maximum Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Output Control Function
Tri-State Input Voltage (Vih and Vil)
Tri-State Output Disable Time
Tri-State Output Enable Time
Disable Current
Spread Spectrum
Modulation Frequency
Period Jitter
Start Up Time
Storage Temperature Range
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
Fine Leak Test
Gross Leak Test
Mechanical Shock
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 1014, Condition A
MIL-STD-883, Method 1014, Condition C
MIL-STD-202, Method 213, Condition C
MIL-STD-202, Method 210
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Rev B 8/12/2010 | Page 1 of 6
EPS13D2C1HE-66.000M TR
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
1
CONNECTION
Tri-State
Case/Ground
Output
Supply Voltage
5.00
±0.15
4
7.00
±0.15
5.08
±0.15
3
1.60 ±0.20
MARKING
ORIENTATION
3.1
1.6
All Tolerances are ±0.1
2.20
±0.15
1
2
1.4 ±0.2
3
4
LINE MARKING
3.68
±0.15
2
1.4 ±0.1
1
2
3
ECLIPTEK
66.000M
SXXYZZ
S=Configuration Designator
XX=Ecliptek Manufacturing
Code
Y=Last Digit of the Year
ZZ=Week of the Year
Suggested Solder Pad Layout
All Dimensions in Millimeters
2.0 (X4)
2.0 (X4)
Solder Land
(X4)
www.ecliptek.com | Specification Subject to Change Without Notice | Rev B 8/12/2010 | Page 2 of 6
EPS13D2C1HE-66.000M TR
OUTPUT WAVEFORM & TIMING DIAGRAM
TRI-STATE INPUT
V
IH
V
IL
CLOCK OUTPUT
V
OH
80% of Waveform
50% of Waveform
20% of Waveform
V
OL
OUTPUT DISABLE
(HIGH IMPEDANCE
STATE)
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.01µF
(Note 1)
0.1µF
(Note 1)
Ground
C
L
(Note 3)
Tri-State or
Power Down
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and V
DD
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev B 8/12/2010 | Page 3 of 6
EPS13D2C1HE-66.000M TR
Tape & Reel Dimensions
Quantity Per Reel: 1,000 units
4.0 ±0.1
2.0 ±0.1
DIA 1.5 +0.1/-0.0
0.3 ±0.05
7.5 ±0.1
16.0
+0.3/-0.1
6.75 ±0.1
A0*
8.0 ±0.1
*Compliant to EIA 481A
B0*
K0*
1.5 MIN
DIA 40 MIN
Access Hole at
Slot Location
22.4 MAX
360 MAX
DIA 50 MIN
DIA 20.2 MIN
2.5 MIN Width
10.0 MIN Depth
Tape slot in Core
for Tape Start
16.4 +2.0/-0.0
DIA 13.0 ±0.2
www.ecliptek.com | Specification Subject to Change Without Notice | Rev B 8/12/2010 | Page 4 of 6
EPS13D2C1HE-66.000M TR
Recommended Solder Reflow Methods
T
P
Critical Zone
T
L
to T
P
Ramp-up
Ramp-down
Temperature (T)
T
L
T
S
Max
T
S
Min
t
S
Preheat
t 25°C to Peak
t
L
t
P
Time (t)
High Temperature Infrared/Convection
T
S
MAX to T
L
(Ramp-up Rate)
Preheat
- Temperature Minimum (T
S
MIN)
- Temperature Typical (T
S
TYP)
- Temperature Maximum (T
S
MAX)
- Time (t
S
MIN)
Ramp-up Rate (T
L
to T
P
)
Time Maintained Above:
- Temperature (T
L
)
- Time (t
L
)
Peak Temperature (T
P
)
Target Peak Temperature (T
P
Target)
Time within 5°C of actual peak (t
p
)
Ramp-down Rate
Time 25°C to Peak Temperature (t)
Moisture Sensitivity Level
3°C/second Maximum
150°C
175°C
200°C
60 - 180 Seconds
3°C/second Maximum
217°C
60 - 150 Seconds
260°C Maximum for 10 Seconds Maximum
250°C +0/-5°C
20 - 40 seconds
6°C/second Maximum
8 minutes Maximum
Level 1
www.ecliptek.com | Specification Subject to Change Without Notice | Rev B 8/12/2010 | Page 5 of 6
嵌入式系统
