EQRD13J2L-195.3125M
REGULATORY COMPLIANCE
2011/65 +
2015/863
(Data Sheet downloaded on Aug 30, 2020)
191 SVHC
ITEM DESCRIPTION
Quartz Crystal Clock Oscillators XO (SPXO) LVPECL (PECL) 3.3Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)
195.3125MHz ±100ppm over -40°C to +85°C
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
195.3125MHz
±100ppm Maximum over -40°C to +85°C (Inclusive of all conditions: Calibration Tolerance (at 25°C), Frequency
Stability over the Operating Temperature Range, Supply Voltage Change, Output Load Change, First Year Aging at
25°C, Shock, and Vibration)
±3ppm Maximum First Year
3.3Vdc ±5%
50mA Maximum
Vdd-1.025Vdc Minimum, 2.35Vdc Typical, Vdd-0.88Vdc Maximum
Vdd-1.81Vdc Minimum, 1.60Vdc Typical, Vdd-1.62Vdc Maximum
400pSec Maximum (Measured at 20% to 80% of Waveform)
50 ±5(%) (Measured at 50% of Waveform)
50 Ohms into Vdd-2.0Vdc
LVPECL
All Values are Typical
-50dBc/Hz at 10Hz Offset
-82dBc/Hz at 100Hz Offset
-116dBc/Hz at 1kHz Offset
-138dBc/Hz at 10kHz Offset
-144dBc/Hz at 100kHz Offset
-149dBc/Hz at 1MHz Offset
-155dBc/Hz at 10MHz Offset
-155dBc/Hz at 20MHz Offset
Standby (on Pad 2)
70% of Vdd Minimum or No Connect to Enable Output and Complementary Output
30% of Vdd Maximum to Disable Output and Complementary Output (High Impedance)
10mSec Maximum
200nSec Maximum
10µA Maximum (Without Load)
200fSec Maximum (Fj=12kHz to 20MHz (Random))
0.2pSec Typical
1.0pSec Typical
1.5pSec Typical
40pSec Maximum
10mSec Maximum
-55°C to +125°C
Aging at 25°C
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Phase Noise
Output Control Function
Output Control Input Voltage Logic
High (Vih)
Output Control Input Voltage Logic
Low (Vil)
Standby Output Enable Time
Standby Output Disable Time
Standby Current
RMS Phase Jitter
Period Jitter (Deterministic)
Period Jitter (Random)
Period Jitter (One Sigma)
Period Jitter (tp-p)
Start Up Time
Storage Temperature Range
www.ecliptek.com | Specification Subject to Change Without Notice | Revision C 06/11/2014 | Page 1 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQRD13J2L-195.3125M
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
Fine Leak Test
Flammability
Gross Leak Test
Mechanical Shock
Moisture Resistance
Moisture Sensitivity
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 3015, Class 1, HBM: 1500V
MIL-STD-883, Method 1014, Condition A
UL94-V0
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 1004
J-STD-020, MSL 1
MIL-STD-202, Method 210, Condition K
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010, Condition B
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Revision C 06/11/2014 | Page 2 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQRD13J2L-195.3125M
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
1
CONNECTION
No Connect
Standby
Case Ground
Output
Complementary Output
Supply Voltage
1.80
±0.10
5.00
±0.20
MARKING
ORIENTATION
2.60 ±0.15
1.2 ±0.2
2.54
TYP
5.08
±0.15
6
5
4
1
2
3
1.4
±0.1
2
3
4
5
6
7.00
±0.20
LINE MARKING
1
2
3
ECLIPTEK
195.31M
XXXXX
XXXXX=Ecliptek
Manufacturing Identifier
Suggested Solder Pad Layout
All Dimensions in Millimeters
1.80 (X6)
2.00 (X6)
0.54 (X4)
1.89
All Tolerances are ±0.1
Solder Land
(X6)
www.ecliptek.com | Specification Subject to Change Without Notice | Revision C 06/11/2014 | Page 3 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQRD13J2L-195.3125M
OUTPUT WAVEFORM & TIMING DIAGRAM
TRI-STATE INPUT
V
IH
V
IL
Q & Q OUTPUTS
V
OH
80%
50%
20%
V
OL
Q
OUTPUT STANDBY
(HIGH IMPEDANCE
STATE)
Q
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
www.ecliptek.com | Specification Subject to Change Without Notice | Revision C 06/11/2014 | Page 4 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQRD13J2L-195.3125M
Test Circuit for Standby (Pad 2) and Complementary Output
50 Ohms
Oscilloscope
Frequency
Counter
Power
Supply
Supply
Voltage
(V
DD
)
Current
Meter
0.01µF
(Note 1)
0.1µF
(Note 1)
Complementary
Output
Standby
Power
Supply
Voltage
Meter
Power
Supply
No
Connect
Probe 2
(Note 2)
Output
Probe 1
(Note 2)
50 Ohms
Switch
Ground
Power
Supply
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high frequency ceramic bypass capacitor close (less than 2mm)
to the package ground and supply voltage pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth (>500MHz) passive probe is
recommended.
Note 3: Test circuit PCB traces need to be designed for a characteristic line impedance of 50 ohms.
www.ecliptek.com | Specification Subject to Change Without Notice | Revision C 06/11/2014 | Page 5 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
