ESD7008, SZESD7008
ESD Protection Diode
Low Capacitance ESD Protection Diode
for High Speed Data Line
The ESD7008 ESD protection diode is designed specifically to
protect four high speed differential pairs. Ultra−low capacitance and
low ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flow−through
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance for the high speed lines.
Features
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MARKING
DIAGRAM
7008MG
G
18
1
UDFN18
CASE 517BV
7008
M
G
•
•
•
•
Integrated 4 Pairs (8 Lines) High Speed Data
Single Connect, Flow through Routing
Low Capacitance (0.12 pF Typical, I/O to GND)
Protection for the Following IEC Standards:
IEC 61000−4−2 Level 4
•
UL Flammability Rating of 94 V−0
•
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
•
This is a Pb−Free Device
Typical Applications
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
ESD7008MUTAG
SZESD7008MUTAG
Package
UDFN18
(Pb−Free)
UDFN18
(Pb−Free)
Shipping
3000 / Tape &
Reel
3000 / Tape &
Reel
•
•
•
•
•
•
V−by−One HS
Thunderbolt (Light Peak)
USB 3.0
HDMI
Display Port
LVDS
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Operating Junction Temperature Range
Storage Temperature Range
Lead Solder Temperature
−
Maximum (10 Seconds)
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
Symbol
T
J
T
stg
T
L
ESD
ESD
Value
−55
to +125
−55
to +150
260
±15
±15
Unit
°C
°C
°C
kV
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
©
Semiconductor Components Industries, LLC, 2016
October, 2017
−
Rev. 7
1
Publication Order Number:
ESD7008/D
ESD7008, SZESD7008
I/O
Pin 1
I/O
Pin 2
I/O
Pin 4
I/O
Pin 5
I/O
Pin 7
I/O
Pin 8
I/O
Pin 10
I/O
Pin 11
GND
Pin 3
GND
Pin 6
GND
Pin 9
GND
Pin 13
GND
Pin 15
GND
Pin 17
Note: Only Minimum of 1 GND connection required
=
Figure 1. Pin Schematic
I/O
I/O
GND
I/O
I/O
GND
I/O
I/O
GND
I/O
I/O
1
18
2
3
4
16
5
6
7
14
8
9
10
12
11
N/C
N/C
13 GND
N/C
N/C
15 GND
N/C
N/C
17 GND
N/C
Figure 2. Pin Configuration
Note: Only minimum of one pin needs to be connected to ground for functional-
ity of all pins. All pins labeled “N/C” should have no electrical connection.
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2
ESD7008, SZESD7008
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (Note 1)
Clamping Voltage (Note 2)
Clamping Voltage
TLP (Note 3)
See Figures 8 through 11
Junction Capacitance
Junction Capacitance
Difference
Symbol
V
RWM
V
BR
I
R
V
C
V
C
V
C
Conditions
I/O Pin to GND (Note 1)
I
T
= 1 mA, I/O Pin to GND
V
RWM
= 5 V, I/O Pin to GND
I
PP
= 1 A, I/O Pin to GND (8 x 20
ms
pulse)
IEC61000−4−2,
±8
kV Contact
I
PP
=
±8
A
I
PP
=
±16
A
V
R
= 0 V, f = 1 MHz between I/O Pins and GND
V
R
= 0 V, f = 1 MHz between I/O Pins and GND
See Figures 3 and 4
13.2
18.2
0.12
0.02
0.15
pF
pF
5.5
6.7
1.0
10
Min
Typ
Max
5.0
Unit
V
V
mA
V
V
C
J
DC
J
1. Surge current waveform per Figure 7.
2. For test procedure see Figures 5 and 6 and application note AND8307/D.
3. ANSI/ESD STM5.5.1
−
Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
0
= 50
W,
t
p
= 100 ns, t
r
= 4 ns, averaging window; t
1
= 30 ns to t
2
= 60 ns.
90
80
70
VOLTAGE (V)
50
40
30
20
10
0
−10
−20
0
20
40
60
80
TIME (ns)
100
120
140
−50
−20
0
20
40
60
80
TIME (ns)
100
120
140
VOLTAGE (V)
60
−10
−20
−30
−40
0
Figure 3. IEC61000−4−2 +8 KV Contact
Clamping Voltage
Figure 4. IEC61000−4−2
−8
KV Contact
Clamping Voltage
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3
ESD7008, SZESD7008
IEC 61000−4−2 Spec.
Test Volt-
age (kV)
2
4
6
8
First Peak
Current
(A)
7.5
15
22.5
30
Current at
30 ns (A)
4
8
12
16
Current at
60 ns (A)
2
4
6
8
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
I @ 30 ns
IEC61000−4−2 Waveform
I
peak
100%
90%
Level
1
2
3
4
Figure 5. IEC61000−4−2 Spec
Device
ESD Gun
Under
Test
Oscilloscope
50
W
Cable
50
W
Figure 6. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D
−
Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
% OF PEAK PULSE CURRENT
90
80
70
60
50
40
30
20
10
0
0
20
t
P
t
r
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
PEAK VALUE I
RSM
@ 8
ms
PULSE WIDTH (t
P
) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8
ms
HALF VALUE I
RSM
/2 @ 20
ms
40
t, TIME (ms)
60
80
Figure 7. 8 x 20
ms
Pulse Waveform
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4
ESD7008, SZESD7008
22
20
18
16
14
12
10
8
6
4
2
0
0
2
4
6
8
10
12
14
16
18
20
22
CURRENT (A)
CURRENT (A)
−22
−20
−18
−16
−14
−12
−10
−8
−6
−4
−2
0
0
2
4
6
8
10
12
14
16
18
20
22
VOLTAGE (V)
VOLTAGE (V)
Figure 8. Positive TLP I−V Curve
Transmission Line Pulse (TLP) Measurement
Figure 9. Negative TLP I−V Curve
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 10. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 11 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
L
50
W
Coax
Cable
S
Attenuator
÷
10 MW
I
M
50
W
Coax
Cable
V
M
V
C
Oscilloscope
DUT
Figure 10. Simplified Schematic of a Typical TLP
System
Figure 11. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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