ESD7382MUT5G
ESD Protection Diode
Micro−Packaged Diodes for ESD Protection
The ESD7382 is designed to protect voltage sensitive components
that require ultra−low capacitance from ESD and transient voltage
events. Excellent clamping capability, low capacitance, low leakage,
and fast response time, make these parts ideal for ESD protection on
designs where board space is at a premium. Because of its low
capacitance, it is suited for use in high frequency designs such as
USB 2.0 high speed and antenna line applications.
Features
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1
Cathode
2
Anode
•
•
•
•
•
•
•
•
•
•
•
Ultra−Low Capacitance: 0.37 pF
Low Clamping Voltage
Small Body Outline Dimensions: 0.60 mm x 0.30 mm
Low Body Height: 0.3 mm
Stand−off Voltage: 5.0 V
Low Leakage
Insertion Loss: 0.030 dBm
Response Time is < 1 ns
Low Dynamic Resistance < 1
W
IEC61000−4−2 Level 4 ESD Protection
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING
DIAGRAM
PIN 1
X3DFN2
CASE 152AF
2
M
M
2
= Specific Device Code
(Rotated 270°)
= Date Code
8:1
X2DFN2
CASE 714AB
(In Development)
XX = Specific Device Code
M = Date Code
G
= Pb−Free Package
XX M
G
Typical Applications
•
RF Signal ESD Protection
•
RF Switching, PA, and Antenna ESD Protection
•
Near Field Communications
MAXIMUM RATINGS
Rating
IEC 61000−4−2 (ESD)
Contact
Air
°P
D
°
R
qJA
T
J
, T
stg
T
L
Symbol
Value
±20
±20
250
400
−40
to +125
260
Unit
kV
mW
°C/W
°C
°C
ORDERING INFORMATION
Device
ESD7382MUT5G
ESD7382N2T5G
(In Development)
Package
X3DFN2
(Pb−Free)
X2DFN2
(Pb−Free)
Shipping
†
10,000 / Tape &
Reel
10,000 / Tape &
Reel
Total Power Dissipation on FR−5 Board
(Note 1) @ T
A
= 25°C
Thermal Resistance, Junction−to−Ambient
Junction and Storage Temperature Range
Lead Solder Temperature
−
Maximum
(10 Second Duration)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
©
Semiconductor Components Industries, LLC, 2017
October, 2017
−
Rev. 3
1
Publication Order Number:
ESD7382/D
ESD7382MUT5G
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
I
PP
V
C
V
RWM
I
R
V
BR
I
T
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
PP
Working Peak Reverse Voltage
Maximum Reverse Leakage Current @ V
RWM
Breakdown Voltage @ I
T
Test Current
I
PP
V
C
V
BR
V
RWM
I
R
V
F
I
T
V
I
F
I
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
Uni−Directional
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage (Note 2)
Reverse Leakage Current
Clamping Voltage (Note 3)
Clamping Voltage (Note 3)
ESD Clamping Voltage
Junction Capacitance
Dynamic Resistance
Insertion Loss
Symbol
V
RWM
V
BR
I
R
V
C
V
C
V
C
C
J
R
DYN
I
T
= 1 mA
V
RWM
= 5.0 V
I
PP
= 1 A
I
PP
= 3 A
Per IEC61000−4−2
V
R
= 0 V, f = 1 Mhz
V
R
= 0 V, f < 1 GHz
TLP Pulse
f = 1 Mhz
f = 8.5 GHz
See Figures 1 and 2
0.37
0.25
0.32
0.030
0.573
0.55
0.55
pF
W
dB
5.2
1.0
8.0
10
Conditions
Min
Typ
Max
5.0
Unit
V
V
mA
V
V
2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
3. Non−repetitive current pulse at T
A
= 25°C, per IEC61000−4−5 waveform.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
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2
ESD7382MUT5G
1.E−02
1.E−03
1.E−04
1.E−05
C (pF)
I1 (A)
1.E−06
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1
2
3
4
V1 (V)
5
6
7
8
9
0
0
0.5
1
1.5
2
VBias (V)
2.5
3
3.5
4
1.E−07
1.E−08
1.E−09
1.E−10
1.E−11
−1
Figure 3. IV Characteristics
1
0
−1
CAPACITANCE (pF)
−2
−3
dB
−4
−5
−6
−7
−8
−9
−10
1.E+06
1.E+07
1.E+08
FREQUENCY (Hz)
1.E+09
1.E+10
0.0
0.E+00
0.5
0.4
0.3
0.2
0.1
0.6
Figure 4. CV Characteristics
3.3 V
0V
5.E+08 1.E+09
2.E+09
2.E+09 3.E+09 3.E+09
FREQUENCY
Figure 5. RF Insertion Loss
Figure 6. Capacitance over Frequency
35
30
25
CURRENT (A)
20
15
10
5
0
0
2
4
6
8
10
12
14
16
18
CURRENT (A)
−35
−30
−25
−20
−15
−10
−5
0
0
−2
−4
−6
−8
−10
−12
−14
VOLTAGE (V)
VOLTAGE (V)
Figure 7. Positive TLP I−V Curve
Figure 8. Negative TLP I−V Curve
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3
ESD7382MUT5G
IEC 61000−4−2 Spec.
Test Volt-
age (kV)
2
4
6
8
First Peak
Current
(A)
7.5
15
22.5
30
Current at
30 ns (A)
4
8
12
16
Current at
60 ns (A)
2
4
6
8
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
I @ 30 ns
IEC61000−4−2 Waveform
I
peak
100%
90%
Level
1
2
3
4
Figure 9. IEC61000−4−2 Spec
Device
ESD Gun
Under
Test
Oscilloscope
50
W
Cable
50
W
Figure 10. Diagram of ESD Test Setup
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
100
% OF PEAK PULSE CURRENT
90
80
70
60
50
40
30
20
10
0
0
20
t
P
t
r
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
PEAK VALUE I
RSM
@ 8
ms
PULSE WIDTH (t
P
) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8
ms
HALF VALUE I
RSM
/2 @ 20
ms
40
t, TIME (ms)
60
80
Figure 11. 8 X 20
ms
Pulse Waveform
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4
ESD7382MUT5G
PACKAGE DIMENSIONS
X3DFN2, 0.62 x 0.32, 0.355P, (0201)
CASE 152AF
ISSUE A
D
PIN 1
INDICATOR
(OPTIONAL)
A B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
DIM
A
A1
b
D
E
e
L2
MILLIMETERS
MIN
MAX
0.25
0.33
−−−
0.05
0.22
0.28
0.58
0.66
0.28
0.36
0.355 BSC
0.17
0.23
TOP VIEW
E
0.05 C
A
2X
0.05 C
A1
SIDE VIEW
C
SEATING
PLANE
RECOMMENDED
MOUNTING FOOTPRINT*
0.74
0.30
2X
e
1
2
2X
b
2X
1
0.31
DIMENSIONS: MILLIMETERS
2X
L2
C A B
BOTTOM VIEW
0.05
M
C A B
0.05
M
See Application Note AND8398/D for more mounting details
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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