Product Brief
May 2005
TruePHY
™
ET1081
Gigabit Ethernet Octal PHY
Introduction
Agere Systems ET1081 is an 8-port gigabit Ethernet
transceiver fabricated on a single CMOS chip. Packaged
in a 388-pin PBGA, the ET1081 is built on 0.13 µm tech-
nology for low power consumption and application in high-
density switches. The 10/100/ 1000Base-T device is fully
compliant with
IEEE
®
802.3, 802.3u, and 802.3ab stan-
dards.
The ET1081 uses an oversampling architecture to gather
more signal energy from the communication channel than
possible with traditional architectures. The additional sig-
nal energy or analog complexity transfers into the digital
domain. The result is an analog front end that delivers
robust operation, reduced cost, and lower power con-
sumption than traditional architectures.
Using oversampling has allowed for the implementation of
a fractionally spaced equalizer, which provides better
equalization and has greater immunity to timing jitter,
resulting in better signal-to-noise ratio (SNR) and
improved BER. In addition, advanced timing algorithms
are used to enable operation over a wider range of cabling
plants.
Features
10Base-T, 100Base-TX, and 1000Base-T gigabit Ether-
net transceiver:
— 388-pin PBGA
— 0.13 µm process
Oversampling architecture to improve signal integrity
and SNR
SGMII or SerDes interfaces to MAC or switch
Low power consumption:
— Less than 750 mW per port in 1000Base-T mode
— Advanced power management
On-chip cable diagnostics
Automatic speed downshift
Optimized, extended performance echo and NEXT fil-
ters
All digital baseline wander correction
Digital PGA control
2.5 V and 1.0 V power supplies
JTAG
Four programmable LEDs per port
TruePHY
ET1081
Gigabit Ethernet Octal PHY
Product Brief
May 2005
Functional Description
Agere Systems ET1081 is an octal port gigabit Ethernet transceiver. Each port simultaneously transmits and
receives on each of the four UTP pairs of category 5 cable (signal dimensions or channels A, B, C, and D) at
125 Msymbols/s using five-level pulse amplitude modulation (PAM). Figure 1 is a block diagram of a single port.
Figure 2 is a block diagram of the octal PHY.
PMA D
PMA C
PMA B
GTX_CLK
TX_CLK
TXD[7:0]
TX_ER
TX_EN
GMII
PCS
PMA A
NEXT
Cancellers
Echo
Canceller
Transmit
Shaping
DAC
Hybrid
TRD_i_[0:3]+/-
Σ
BLW
Correction
FFE
ADC
PGA
RX_CLK
RXD[7:0]
RX_ER
RX_DV
COL
CRS
Gain
Control
Bias
Trellis
Decoder
Timing
Control
Clock
Generator
10BASE-T
Diagnostics
MDC
MDIO
MDINT_N
LED_A:D_i
Management
Interface
LEDS/Config
MI Registers
Auto-
Negotiation
Figure 1. ET1081 Single-Port Block Diagram
2
Agere Systems Inc.
Product Brief
May 2005
TruePHY
ET1081
Gigabit Ethernet Octal PHY
Functional Description
(continued)
SGMII_0P/N
SGMII_1P/N
SGMII_2P/N
SGMII_3P/N
SGMII_4P/N
SGMII_5P/N
SGMII_6P/N
SGMII_7P/N
IOREF_P/N
MDINT_N
MDC
MDIO
CLKSEL_LVDS
CLKIN_N
CLKIN_P / CLKIN
RESET_N
TCK
TRST_N
TMS
TDI
TDO
TDR_SEL
LED_A/B_[0:7]
LED_SER
JTAG/
Test
SGMII/SerDes
Management
Interface
Bias
Clock
LEDS/ Config/
LED Serial
PHY Port 0
PHY Port 7
GMII
GMII
PHY Digital
AFE
Reset / POR
TRD_0_[0:3]+/-
AFE
PHY Digital
TRD_7_[0:3]+/-
PHY Port 1
PHY Port 6
GMII
GMII
PHY Digital
AFE
TRD_1_[0:3]+/-
AFE
PHY Digital
TRD_6_[0:3]+/-
PHY Port 2
PHY Port 5
GMII
GMII
PHY Digital
AFE
TRD_2_[0:3]+/-
AFE
PHY Digital
TRD_5_[0:3]+/-
PHY Port 3
PHY Port 4
GMII
GMII
PHY Digital
AFE
TRD_3_[0:3]+/-
AFE
PHY Digital
TRD_4_[0:3]+/-
RSET_0
Bias
Bias
RSET_1
Figure 2. ET1081 Block Diagram
Oversampling Architecture
The ET1081 architecture uses oversampling techniques to sample at two times the symbol rate. A fractionally
spaced, feed-forward equalizer (FFE) adapts to remove intersymbol interference (ISI) and to shape the spectrum
of the received signal to maximize the (SNR) at the trellis decoder input. The FFE equalizes the channel to a fixed
target response. Oversampling enables the use of a fractionally spaced equalizer (FSE) structure for the FFE,
resulting in symbol rate clocking for both the FFE and the rest of the receiver. This provides robust operation and
substantial power savings.
Agere Systems Inc.
3
TruePHY
ET1081
Gigabit Ethernet Octal PHY
Product Brief
May 2005
Receive Functions
Decoder 1000Base-T
In 1000Base-T mode, the PMA recovers the 4D PAM
signals after compensating for the cabling conditions.
The resulting code group is decoded to 8-bit data. Data
stream delimiters are translated appropriately, and the
data is output to the receive data pins of the MAC inter-
faces. The GMII receive error signal is asserted when
invalid code groups are detected in the data stream.
Decoder 100Base-TX
In 100Base-TX mode, the PMA recovers the three-
level MLT3 sequence that is descrambled and 5B/4B
decoded to 4-bit data. This is output to the MII receive
data pins after data stream delimiters have been trans-
lated appropriately. The MII receive error signal is
asserted when invalid code groups are detected in the
data stream.
Decoder 10Base-T
In 10Base-T mode, the ET1081 decodes the Manches-
ter-encoded received signal.
Hybrid
The hybrid subtracts the transmitted signal from the
input signal allowing full-duplex operation on each of
the twisted-pair cables.
Programmable Gain Amplifier (PGA)
The PGA operates on the received signal in the analog
domain prior to the analog-to-digital converter (ADC).
The gain control module monitors the signal at the out-
put of the ADC in the digital domain to control the PGA.
It implements a gain that maximizes the signal at the
ADC while ensuring that no hard clipping occurs.
Clock Generator
The Octal PHY has a 25 MHz input clock. This clock is
common to all eight ports. Each port has a clock gener-
ator circuit that uses the input clock signal and a
phase-locked loop (PLL) circuit to generate all the
required internal analog and digital clocks. This circuit
is controlled by the timing control module.
Analog-to-Digital Converter
The ADC operates at 250 MHz oversampling at twice
the symbol rate in 1000Base-T and 100Base-TX. This
enables innovative timing recovery and fractional skew
correction and has allowed transfer of analog complex-
ity to the digital domain.
Agere Systems Inc.
Functional Description
(continued)
Automatic Speed Downshift
Automatic speed downshift is an enhanced feature of
autonegotiation that allows the ET1081 to:
Fallback in speed, based on cabling conditions or
link partner abilities.
Operate over CAT-3 cabling (in 10Base-T mode).
Operate over two-pair CAT-5 cabling (in 100Base-TX
mode).
For speed fallback, the ET1081 first tries to autonegoti-
ate by advertising 1000Base-T capability. After a num-
ber of failed attempts to bring up the link, the ET1081
falls back to advertising 100Base-TX and restarts the
autonegotiation process. This process continues
through all speeds down to 10Base-T. At this point,
there are no lower speeds to try and so the host
enables all technologies and starts again.
PHY configuration register, address 22, bits 11 and 10
enable automatic speed downshift and specifies if fall-
back to 10Base-T is allowed. PHY control register,
address 23, bits 11 and 12 specify the number of failed
attempts before downshift (programmable to 1, 2, 3, or
4 attempts).
Transmit Functions
1000Base-T Encoder
In 1000Base-T mode, the ET1081 translates 8-bit data
from the MAC interfaces into a code group of four qui-
nary symbols that are then transmitted by the PMA as
4D five-level PAM signals over the four pairs of CAT-5
cable.
100Base-TX Encoder
In 100Base-TX mode, 4-bit data from the media-inde-
pendent interface (MII) is 4B/5B encoded to output
5-bit serial data at 125 MHz. The bit stream is sent to a
scrambler, and then encoded to a three-level MLT3
sequence that is then transmitted by the PMA.
10Base-T Encoder
In 10Base-T mode, the ET1081 transmits and receives
Manchester-encoded data.
4
Product Brief
May 2005
TruePHY
ET1081
Gigabit Ethernet Octal PHY
receiver gradually dies away. This effect is called base-
line wander. By employing a circuit that continuously
monitors and compensates for this effect, the probabil-
ity of encountering a receive symbol error is reduced.
Functional Description
(continued)
Receive Functions
(continued)
Timing Recovery/Generation
The timing recovery and generator block creates the
transmit and receive clocks for all modes of operation.
In transmit mode, the 10Base-T and 100Base-TX
modes use the clock input. While in receive mode, the
input clock is locked to the receive data stream.
1000Base-T is implemented using a master-slave tim-
ing scheme, where the master transmit and receive are
locked to the clock input, and the slave acquires timing
information from the receive data stream. Timing
recovery is accomplished by first acquiring lock on one
channel and then making use of the constant phase
relationship between channels to lock on the other
pairs, resulting in a simplified PLL architecture. Timing
shifts due to changing environmental conditions are
tracked by the ET1081.
Adaptive Fractionally Spaced Equalizer
The ET1081's unique oversampling architecture
employs an FSE in place of the traditional FFE struc-
ture. This results in robust equalization of the commu-
nications channel, which translates to superior bit error
rate (BER) performance over the widest variety of
worst-case cabling scenarios. The all-digital equalizer
automatically adapts to changing conditions.
Echo and Crosstalk Cancellers
Since the four twisted pairs are bundled together and
not insulated from each other in gigabit Ethernet, each
of the transmitted signals is coupled onto the three
other cables and is seen at the receiver as near-end
crosstalk (NEXT). A hybrid circuit is used to transmit
and receive simultaneously on each pair. If the trans-
mitter is not perfectly matched to the line, a signal com-
ponent will be reflected back as an echo. Reflections
can also occur at other connectors or cable imperfec-
tions. The ET1081 cancels echo and NEXT by sub-
tracting an estimate of these signals from the equalizer
output.
Baseline Wander Correction
A known issue for 1000Base-T and 100Base-TX is that
the transformer attenuates at low frequencies. As a
result, when a large number of symbols of the same
sign are transmitted consecutively, the signal at the
Autonegotiation
Autonegotiation is implemented in accordance with
IEEE
802.3. The device supports 10Base-T, 100Base-
TX, and 1000Base-T and can autonegotiate between
them in either half- or full-duplex mode. It can also par-
allel detect 10Base-T or 100Base-TX. If autonegotia-
tion is disabled, a 10Base-T or 100Base-TX link can be
manually selected via the
IEEE
MI registers.
Pair Skew Correction
In gigabit Ethernet, pair skew (timing differences
between pairs of cable) can result from differences in
length or manufacturing variations between the four
individual twisted-pair cables. The ET1081 automati-
cally corrects for both integer and fractional symbol tim-
ing differences between pairs.
Automatic MDI Crossover
During autonegotiation, the ET1081 automatically
detects and sets the required MDI configuration so that
the remote transmitter is connected to the local
receiver and vice versa. This eliminates the need for
crossover cables or crosswired (MDIX) ports. If the
remote device also implements automatic MDI cross-
over, and/or the crossover is implemented in the cable,
the crossover algorithm ensures that only one element
implements the required crossover.
Polarity Inversion Correction
In addition to automatic MDI crossover that is neces-
sary for autonegotiation, 10Base-T, and 100Base-TX
operation, the ET1081 automatically corrects crossover
of the additional two pairs used in 1000Base-T. Polarity
inversion on all pairs is also corrected. Both of these
effects may arise if the cabling has been incorrectly
wired.
Agere Systems Inc.
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