Changes to Dynamic Input Current Parameter, Table 1 ..............3
1/2011—Rev. B to Rev. C
Changes to Features Section ............................................................1
Changes to Input-to-Output Momentary Withstand Voltage
Parameter, Table 3, UL Column, Table 4, and Note 1, Table 4...........5
Changes to Ordering Guide .................................................................... 18
9/2007—Rev. A to Rev. B
Updated VDE Certification Throughout ......................................1
Changes to Table 6.............................................................................7
12/2006—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to Table 6.............................................................................7
Changes to Analog Input Section................................................. 13
Changes to Figure 26...................................................................... 15
1/2006—Revision 0: Initial Version
Rev. H | Page 2 of 20
Data Sheet
SPECIFICATIONS
V
DD1
= 4.5 V to 5.25 V, V
DD2
= 3 V to 5.5 V, V
IN
+ = −200 mV to +200 mV, and V
IN
− = 0 V (single-ended); T
A
= T
MIN
to T
MAX
,
f
MCLK
= 10 MHz, tested with Sinc
3
filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted.
1
Table 1.
Parameter
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
3
Differential Nonlinearity
3
Offset Error
3
Offset Drift vs. Temperature
Offset Drift vs. V
DD1
Gain Error
3
Gain Error Drift vs. Temperature
Gain Error Drift vs. V
DD1
ANALOG INPUT
Input Voltage Range
Dynamic Input Current
Input Capacitance
DYNAMIC SPECIFICATIONS
Signal-to-(Noise + Distortion) Ratio (SINAD)
3
Y Version
1,
2
16
±15
±25
±0.9
±0.5
±50
3.5
1
120
±1
23
110
±200
±8
±0.5
10
70
65
79
71
−88
−88
11.5
25
30
V
DD2
− 0.1
0.4
4.5/5.25
3/5.5
13
6
4
Unit
Bits min
LSB max
LSB max
LSB max
mV max
µV typ
µV/°C max
µV/°C typ
µV/V typ
mV max
µV/°C typ
µV/V typ
mV min/mV max
µA max
µA typ
pF typ
dB min
dB min
dB typ
dB min
dB typ
dB typ
Bits
kV/µs min
kV/µs typ
V min
V max
V min/V max
V min/V max
mA max
mA max
mA max
Test Conditions/Comments
AD7400
Filter output truncated to 16 bits
−40°C to +85°C; ±2 LSB typical
>85°C to 105°C
Guaranteed no missing codes to 16 bits
T
A
= 25°C
−40°C to +105°C
−40°C to +105°C
For specified performance; full range ±320 mV
V
IN
+ = 400 mV, V
IN
− = 0 V
V
IN
+ = V
IN
− = 0 V
V
IN
+ = 35 Hz, 400 mV p-p sine
−40°C to +85°C
>85°C to 105°C
−40°C to +105°C
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
3
Peak Harmonic or Spurious Noise (SFDR)
3
Effective Number of Bits (ENOB)
3
Isolation Transient Immunity
3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
POWER REQUIREMENTS
V
DD1
V
DD2
I
DD14
I
DD25
Temperature range is −40°C to +85°C.
All voltages are relative to their respective ground.
3
See the Terminology section.
4
See Figure 14.
5
See Figure 15.
1
2
I
O
= −200 µA
I
O
= +200 µA
V
DD1
= 5.25 V
V
DD2
= 5.5 V
V
DD2
= 3.3 V
Rev. H | Page 3 of 20
AD7400
TIMING SPECIFICATIONS
V
DD1
= 4.5 V to 5.25 V, V
DD2
= 3 V to 5.5 V, T
A
= T
MAX
to T
MIN
, unless otherwise noted.
1
Table 2.
Parameter
f
MCLKOUT2
t
13
t
2 3
t
3
t
4
1
2
Data Sheet
Limit at T
MIN
, T
MAX
10
9/11
40
10
0.4 × t
MCLKOUT
0.4 × t
MCLKOUT
Unit
MHz typ
MHz min/MHz max
ns max
ns min
ns min
ns min
Description
Master clock output frequency
Master clock output frequency
Data access time after MCLK rising edge
Data hold time after MCLK rising edge
Master clock low time
Master clock high time
Sample tested during initial release to ensure compliance.
Mark space ratio for clock output is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
200µA
I
OL
TO OUTPUT
PIN
+1.6V
C
L
25pF
200µA
I
OH
04718-002
Figure 2. Load Circuit for Digital Output Timing Specifications
t
4
MCLKOUT
04718-003
t
1
MDAT
t
2
t
3
Figure 3. Data Timing
Rev. H | Page 4 of 20
Data Sheet
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 3.
Parameter
Input-to-Output Momentary Withstand Voltage
Minimum External Air Gap (Clearance)
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
1
2
AD7400
Symbol
V
ISO
L(I01)
L(I02)
Value
5000 min
7.8
1, 2
min
7.8
1, 2
min
0.017
min
>400
II
Unit
V rms
mm
mm
mm
V
Conditions
1-minute duration
Measured from input terminals to output
terminals, shortest distance through air
Measured from input terminals to output
terminals, shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material group (DIN VDE 0110, 1/89, Table 1)
CTI
In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 m.
Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained.
REGULATORY INFORMATION
Table 4.
UL
1
Recognized Under 1577
Component Recognition
Program
1
5000 V rms Isolation Voltage
CSA
Approved under CSA Component
Acceptance Notice 5A
Basic insulation per CSA 60950-1-07 and
IEC 60950-1, 780 V rms maximum
working voltage
Reinforced insulation per CSA
60950-1-03 and IEC 60950-1, 390 V
rms maximum working voltage
File 205078
VDE
2
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
2
Reinforced insulation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12, 891V peak
File E214100
1
2
File 2471900-4880-0001
In accordance with UL 1577, each AD7400 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA).
In accordance with DIN V VDE V 0884-10, each AD7400 is proof tested by applying an insulation test voltage ≥ 1671 V peak for 1 second (partial discharge detection
Microchip MCU
