Changes to Specifications ................................................................ 3
Changes to Table 6.......................................................................... 12
Changes to Table 7.......................................................................... 13
Changes to Table 9.......................................................................... 15
8/03—Revision 0: Initial Version
Rev. A | Page 2 of 24
ADF4360-1
SPECIFICATIONS
1
AV
DD
= DV
DD
= V
VCO
= 3.3 V ± 10%; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency
REF
IN
Input Sensitivity
REF
IN
Input Capacitance
REF
IN
Input Current
PHASE DETECTOR
Phase Detector Frequency
2
CHARGE PUMP
I
CP
Sink/Source
3
High Value
Low Value
R
SET
Range
I
CP
3-State Leakage Current
Sink and Source Current Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
LOGIC INPUTS
V
INH,
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
/I
INL
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
I
OH
, Output High Current
V
OL
, Output Low Voltage
POWER SUPPLIES
AV
DD
DV
DD
V
VCO
AI
DD4
DI
DD4
I
VCO4, 5
I
RFOUT4
Low Power Sleep Mode
4
RF OUTPUT CHARACTERISTICS
5
VCO Output Frequency
VCO Sensitivity
Lock Time
6
Frequency Pushing, (Open Loop)
Frequency Pulling, (Open Loop)
Harmonic Content (Second)
Harmonic Content (Third)
Output Power
5, 7
Output Power Variation
VCO Tuning Range
B Version
10/250
0.7/AV
DD
0 to AV
DD
5.0
±100
8
Unit
MHz min/max
p-p min/max
V max
pF max
µA max
MHz max
With R
SET
= 4.7 kΩ.
2.5
0.312
2.7/10
0.2
2
1.5
2
1.5
0.6
±1
3.0
DV
DD
– 0.4
500
0.4
3.0/3.6
AV
DD
AV
DD
10
2.5
24.0
3.5–11.0
7
2050/2450
57
400
6
15
−20
−35
−13/−6
±3
1.25/2.5
mA typ
mA typ
kΩ
nA typ
% typ
% typ
% typ
V min
V max
µA max
pF max
V min
µA max
V max
V min/V max
CMOS output chosen.
I
OL
= 500 µA.
Conditions/Comments
For f < 10 MHz, use a dc-coupled CMOS compatible
square wave, slew rate > 21 V/µs.
AC-coupled.
CMOS compatible.
1.25 V ≤ V
CP
≤ 2.5 V.
1.25 V ≤ V
CP
≤ 2.5 V.
V
CP
= 2.0 V.
mA typ
mA typ
mA typ
mA typ
µA typ
MHz min/max
MHz/V typ
µs typ
MHz/V typ
kHz typ
dBc typ
dBc typ
dBm typ
dB typ
V min/max
I
CORE
= 15 mA.
RF output stage is programmeable.
I
CORE
= 15 mA.
To within 10 Hz of final frequency.
Into 2.00 VSWR load.
Programmable in 3 dB steps. Table 7.
For tuned loads, see Output Matching section.
Rev. A | Page 3 of 24
ADF4360-1
Parameter
NOISE CHARACTERISTICS
1, 5
VCO Phase Noise Performance
8
B Version
−110
−130
−141
−148
−172
−163
−147
−81
0.72
−70
Unit
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Degrees typ
dBc typ
Conditions/Comments
@ 100 kHz offset from carrier.
@ 1 MHz offset from carrier.
@ 3 MHz offset from carrier.
@ 10 MHz offset from carrier.
@ 25 kHz PFD frequency.
@ 200 kHz PFD frequency.
@ 8 MHz PFD frequency.
@ 1 kHz offset from carrier.
100 Hz to 100 kHz.
Synthesizer Phase Noise Floor
9
In-Band Phase Noise
10, 11
RMS Integrated Phase Error
12
Spurious Signals due to PFD Frequency
11, 13
1
2
Operating temperature range is: –40°C to +85°C.
Guaranteed by design. Sample tested to ensure compliance.
3
I
CP
is internally modified to maintain constant-loop gain over the frequency range.
4
T
A
= 25°C; AV
DD
= DV
DD
= V
VCO
= 3.3 V; P = 32.
5
These characteristics are guaranteed for VCO Core Power = 15 mA.
6
Jumping from 2.05 GHz to 2.45 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7
Using 50 Ω resistors to V
VCO
, into a 50 Ω load. For tuned loads, see Output Matching section.
8
The noise of the VCO is measured in open-loop conditions.
9
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log
N
(where
N
is the N divider value).
10
The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the
synthesizer; offset frequency = 1 kHz.
11
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; N = 12500; Loop B/W = 10 kHz.
12
f
REFIN
= 10 MHz; f
PFD
= 1 MHz; N = 2400; Loop B/W = 25 kHz.
13
The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer; f
REFOUT
= 10 MHz @ 0 dBm.
Rev. A | Page 4 of 24
ADF4360-1
TIMING CHARACTERISTICS
AV
DD
= DV
DD
= V
VCO
= 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; T